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Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.
Shweta Chary
,
Michael L. Bushnell
Venue
National
VLSID
Year
2006
Proceedings
VLSI Design
DBLP record
conf/vlsid/CharyB06a ↗
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