| 2008 | VLSID | A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
| 2008 | VTS | Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
| 2007 | ISCAS | Power Grid Analysis of Dynamic Power Cutoff Technology. | Baozhen Yu, Michael L. Bushnell |
| 2007 | ITC | SPARTAN: a spectral and information theoretic approach to partial-scan. | Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal |
| 2007 | VLSID | Analog Circuit Testing Using Auto Regressive Moving Average Models. | Jeffrey Ayres, Michael L. Bushnell |
| 2007 | VLSID | Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. | Suresh Kumar Devanathan, Michael L. Bushnell |
| 2007 | VLSID | Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. | Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie |
| 2007 | VLSID | Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. | Rohit Pandey, Michael L. Bushnell |
| 2007 | VLSID | A Neural Net Branch Predictor to Reduce Power. | Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell |
| 2007 | VLSID | Zero Cost Test Point Insertion Technique for Structured ASICs. | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
| 2006 | ISLPED | A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. | Baozhen Yu, Michael L. Bushnell |
| 2006 | VLSID | Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. | Shweta Chary, Michael L. Bushnell |
| 2006 | VLSID | Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. | Shweta Chary, Michael L. Bushnell |
| 2006 | VLSID | Sequential Spectral ATPG Using the Wavelet Transform and Compaction. | Suresh Kumar Devanathan, Michael L. Bushnell |
| 2006 | VLSID | Aliasing Analysis of Spectral Statistical Response Compaction Techniques. | Omar I. Khan, Michael L. Bushnell |
| 2006 | VLSID | An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
| 2005 | VLSID | Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. | Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
| 2005 | VLSID | Variable Input Delay CMOS Logic for Low Power Design. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2004 | ITC | Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. | Omar I. Khan, Michael L. Bushnell |
| 2004 | ITC | On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. | Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal |
| 2004 | VLSID | A Tuturial on the Emerging Nanotechnology Devices. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2004 | VLSID | CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2003 | VLSID | A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. | Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
| 2003 | VLSID | Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2003 | VLSID | New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
| 2002 | ITC | Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
| 2002 | VLSID | Electronic Testing for SOC Designers (Tutorial Abstract). | Vishwani D. Agrawal, Michael L. Bushnell |
| 2001 | VLSID | A Code Transition Delay Model for ADC Test. | Sanjay Mohan, Michael L. Bushnell |
| 1999 | ITC | Increasing Test Coverage in a VLSI Design Course. | Michael L. Bushnell |
| 1999 | VLSID | Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. | Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss |
| 1999 | VLSID | A Complete Characterization of Path Delay Faults through Stuck-at Faults. | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
| 1998 | ITC | A non-enumerative path delay fault simulator for sequential circuits. | Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu |
| 1998 | VLSID | Path Delay Testing: Variable-Clock Versus Rated-Clock. | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
| 1998 | VTS | Effect of Noise on Analog Circuit Testing. | Madhu K. Iyer, Michael L. Bushnell |
| 1998 | VTS | On Delay-Untestable Paths and Stuck-Fault Redundancy. | Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell |
| 1998 | VTS | Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. | Ganapathy Parthasarathy, Michael L. Bushnell |
| 1997 | VLSID | Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. | Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | ITC | An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | VLSID | Parallel concurrent path-delay fault simulation using single-input change patterns. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | VLSID | Statistical path delay fault coverage estimation for synchronous sequential circuits. | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
| 1996 | VLSID | Test generation for mixed-signal devices using signal flow graphs. | Rajesh Ramadoss, Michael L. Bushnell |
| 1995 | ITC | Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1995 | VLSID | Generation of search state equivalence for automatic test pattern generation. | Xinghao Chen, Michael L. Bushnell |
| 1995 | VLSID | Statistical methods for delay fault coverage analysis. | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
| 1995 | VLSID | A graph approach to DFT hardware placement for robust delay fault BIST. | Imtiaz P. Shaik, Michael L. Bushnell |
| 1995 | VLSID | An asynchronous algorithm for sequential circuit test generation on a network of workstations. | James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal |
| 1995 | VTS | Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . | Imtiaz P. Shaik, Michael L. Bushnell |
| 1994 | DAC | An Efficient Path Delay Fault Coverage Estimator. | Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal |
| 1994 | VLSID | Graphical Methodology Language for CAD Frameworks. | James Sienicki, Michael L. Bushnell, Sandip Parikh |
| 1994 | VTS | Neural models for transistor and mixed-level test generation. | Carolina L. C. Cooper, Michael L. Bushnell |
| 1994 | VTS | FACTS: fault coverage estimation by test vector sampling. | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
| 1993 | DAC | Design for Testability for Path Delay faults in Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1992 | DAC | Delay Fault Models and Test Generation for Random Logic Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1991 | ITC | Search State Equivalence for Redundancy Identification and Test Generation. | John Giraldi, Michael L. Bushnell |
| 1990 | DAC | MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. | Daniel R. Brasen, Michael L. Bushnell |
| 1990 | DAC | Automatic Test Generation Using Quadratic 0-1 Programming. | Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell |
| 1990 | DAC | EST: The New Frontier in Automatic Test-Pattern Generation. | John Giraldi, Michael L. Bushnell |
| 1988 | DAC | A Module Area Estimator for VLSI Layout. | Xinghao Chen, Michael L. Bushnell |
| 1988 | ICCAD | Automatic test generation using neural networks. | Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal |
| 1986 | DAC | VLSI CAD tool integration using the Ulysses environment. | Michael L. Bushnell, Stephen W. Director |