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Paper
Open Computation Tree Logic for Formal Verification of Modules.
Pallab Dasgupta
,
Arindam Chakrabarti
,
P. P. Chakrabarti
Venue
National
VLSID
Year
2002
Proceedings
ASP-DAC/VLSI Design
DBLP record
conf/vlsid/DasguptaCC02 ↗
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