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P. P. Chakrabarti

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

49

Venues

18

Active years

1994–2017

Best venue rank

A*

Where they publish

Papers

49 indexed papers, newest first.

YearVenueTitleAuthors
2017VLSIDMigration Aware Low Overhead ERfair Scheduler.Anshuman Tripathi, Arnab Sarkar, P. P. Chakrabarti
2015APSECTiming Analysis of Safety-Critical Automotive Software: The AUTOSAFE Tool Flow.Martin Becker, Sajid Mohamed, Karsten Albers, P. P. Chakrabarti, Samarjit Chakraborty, Pallab Dasgupta, Soumyajit Dey, Ravindra Metta
2013ICDMA Mobility Simulation Framework Of Humans With Group Behavior Modeling.Anshul Gupta, Aurosish Mishra, Satya Gautam Vadlamudi, P. P. Chakrabarti, Sudeshna Sarkar, Tridib Mukherjee, Nathan Gnanasambandam
2012VLSIDPanel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota
2012SoCSExecution Ordering in AND/OR Graphs with Failure Probabilities.Priyankar Ghosh, P. P. Chakrabarti, Pallab Dasgupta
2011DSNA framework for early stage quality-fault tolerance analysis of embedded control systems.Satya Gautam Vadlamudi, P. P. Chakrabarti, Dipankar Das, Purnendu Sinha
2010ECAIContract Search: Heuristic Search under Node Expansion Constraints.Sandip Aine, P. P. Chakrabarti, Rajeev Kumar
2010ISAIMAn analysis of breadth-first beam search using uniform cost trees.Sandip Aine, P. P. Chakrabarti
2010VLSIDSafe-ERfair.Arnab Sarkar, Rahul Nanda, Sujoy Ghose, P. P. Chakrabarti
2007IJCAIAWA* - A Window Constrained Anytime Heuristic Search Algorithm.Sandip Aine, P. P. Chakrabarti, Rajeev Kumar
2007VLSIDOnline Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors.Pravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar
2007VLSIDSimulation Based Verification using Temporally Attributed Boolean Logic.Subrat Kumar Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar
2007VLSIDA New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti
2007VLSIDBounded Delay Timing Analysis Using Boolean Satisfiability.Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta
2006APSECTiming Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications.Dipankar Das, Rajeev Kumar, P. P. Chakrabarti
2006DATEWhat lies between design intent coverage and model checking?Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti
2006DATESynthesis of system verilog assertions.Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti
2006FDLSystemC Modeling and Validation of A RISC Processor System.Rajeev Kumar, Rahul Chaudhry, Dipankar Das, Vibha Rathi, Subrat Kumar Panda, P. P. Chakrabarti
2006ISCASA model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits.Abhishek Somani, P. P. Chakrabarti, Amit Patra
2006MEMOCODEFormal methods for checking realizability of coalitions in 3-party systems.Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
2006VLSIDImproving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control.Sandip Aine, P. P. Chakrabarti, Rajeev Kumar
2006VLSIDInstruction-Set-Extension Exploration Using Decomposable Heuristic Search.Samik Das, P. P. Chakrabarti, Pallab Dasgupta
2006VLSIDFrame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems.Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar
2005CISAn Adaptive Framework for Solving Multiple Hard Problems Under Time Constraints.Sandip Aine, Rajeev Kumar, P. P. Chakrabarti
2005EMOMultiobjective EA Approach for Improved Quality of Solutions for Spanning Tree Problem.Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti
2005VLSIDSyntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules.Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti
2005VLSIDFormal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
2005VLSIDDictionary Based Code Compression for Variable Length Instruction Encodings.Dipankar Das, Rajeev Kumar, P. P. Chakrabarti
2005VLSIDA Verification System for Transient Response of Analog Circuits Using Model Checking.Tathagato Rai Dastidar, P. P. Chakrabarti
2005VLSIDA Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits.Abhishek Somani, P. P. Chakrabarti, Amit Patra
2004DATEFormal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
2004DATEA New Approach to Timing Analysis Using Event Propagation and Temporal Logic.Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal
2004HiPCImproved Quality of Solutions for Multiobjective Spanning Tree Problem Using Distributed Evolutionary Algorithm.Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti
2004ICCADFormal verification coverage: computing the coverage gap between temporal specifications.Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
2004ICONIPMultiobjective Genetic Search for Spanning Tree Problem.Rajeev Kumar, Pramod Kumar Singh, P. P. Chakrabarti
2004MEMOCODEThe BUSpec platform for automated generation of verification aids for standard bus protocols.Bhaskar Pal, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
2004VLSIDFormal Verification of Modules under Real Time Environment Constraints.Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti
2004VLSIDProperty Refinement Techniques for Enhancing Coverage of Formal Property Verification.Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan
2002DACFormal verification of module interfaces against real time specifications.Arindam Chakrabarti, Pallab Dasgupta, P. P. Chakrabarti, Ansuman Banerjee
2002ISCASTiming analysis of tree-like RLC circuits.Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti
2002VLSIDOpen Computation Tree Logic for Formal Verification of Modules.Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti
2001DATEAbstraction of word-level linear arithmetic functions from bit-level component descriptions.Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti
2001ISCASAbstractions for model checking of event timings.Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti
2001ISCASSymbolic verification of Boolean constraints over partially specified functions.S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti
1999VLSIDExploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams.Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti
1999VLSIDAn Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti
1997VLSIDDesign Space Exploration for Data Path Synthesis.Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
1996VLSIDAllocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
1994VLSIDMultiobjective Search in VLSI Design.Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar