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Paper
A Capacitorless On-Chip LDO for Jitter Reduction in 7.2 Gbps HBM3E PHY Clock Network with Aging and Power Delivery Analysis.
Javed S. Gaggatur
Venue
National
VLSID
Year
2026
Proceedings
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DBLP record
conf/vlsid/Gaggatur26 ↗
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