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Javed S. Gaggatur

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

3

Active years

2015–2026

Best venue rank

National

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2026VLSIDA Capacitorless On-Chip LDO for Jitter Reduction in 7.2 Gbps HBM3E PHY Clock Network with Aging and Power Delivery Analysis.Javed S. Gaggatur
2025VLSIDA 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction.Aakash Hasmukhray Mehta, Javed S. Gaggatur, Mohammad M. Rashid, Sampath Dakshinamurthy, Aruna Kumar Lakya Srinivasamurthy, Anil Kumar Goyal, Subbarao Manam, Harshit Gupta, Sandeep Sukumar, Vipin K. Mishra, Koushik N. S, Santosh Nekkanti, Sambaran Mitra, Pooja K. Jadhav, Miryala Chandra Shekar, Dudekula Humayun, Michael C. Rifani, Jianyong Xie, Andrew P. Collins
2022VLSIDA 0.009mmJaved S. Gaggatur, Miryala Chandra Shekar, Komal Deshmukh
2021VLSIDA 1.8 - 6.3 GHz Quadrature Ring VCO-based Fast-settling PLL for Wireline I/O in 55nm CMOS.Javed S. Gaggatur
2019VLSIDA 75-W 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application.Kundan Kumar, Raghunath K. P, Akshay Muraleedharan, Javed S. Gaggatur, Gaurab Banerjee
2017VLSIDHigh Gain Capacitance Sensor Interface for the Monitoring of Cell Volume Growth.Javed S. Gaggatur, Gaurab Banerjee
2017VLSIDOn-Chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power Amplifier.Javed S. Gaggatur, Immanuel Raja, Gaurab Banerjee
2016ISCASA 3.2 mW 0.13 μm high sensitivity frequency-domain CMOS capacitance interface.Javed S. Gaggatur, Pradeep K. Dixena, Gaurab Banerjee
2015IECONNovel spike-based architecture for RFID and Sensor communication system.Manjunath Machnoor, Javed S. Gaggatur, K. Sanjeev