A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction.

Aakash Hasmukhray Mehta, Javed S. Gaggatur, Mohammad M. Rashid, Sampath Dakshinamurthy, Aruna Kumar Lakya Srinivasamurthy, Anil Kumar Goyal, Subbarao Manam, Harshit Gupta, Sandeep Sukumar, Vipin K. Mishra, Koushik N. S, Santosh Nekkanti, Sambaran Mitra, Pooja K. Jadhav, Miryala Chandra Shekar, Dudekula Humayun, Michael C. Rifani, Jianyong Xie, Andrew P. Collins

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