Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
VLSID
/
Paper
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.
Irith Pomeranz
,
Sudhakar M. Reddy
Venue
National
VLSID
Year
2002
Proceedings
ASP-DAC/VLSI Design
DBLP record
conf/vlsid/PomeranzR02 ↗
Browse the full
VLSID paper archive
.