| 2026 | ETS | Advances in Testing and Reliability Benchmarks. | Francesco Angione, Paolo Bernardi, Nicola Di Gruttola Giardino, Gabriele Filipponi, Giusy Iaria, Giacomo Perlo, Irith Pomeranz, Antonio Porsia, Annachiara Ruospo, Ernesto Snchez, Vittorio Turco |
| 2026 | VTS | Late Breaking Results - Diagnostic Test Templates for Two-Cycle Gate-Exhaustive Faults. | Irith Pomeranz |
| 2026 | VTS | Late Breaking Results - Close-to-Functional Tests for Two-Cycle Interconnect Faults. | Irith Pomeranz |
| 2026 | VTS | Late Breaking Results - Test Selection for In-Field Testing Using a Two-Dimensional Aging Space. | Irith Pomeranz, Subashini Gopalsamy, Arani Sinha, Yonsang Cho |
| 2025 | ITC | Functional Logic Diagnosis with Observation Points on Next-State Variables. | Irith Pomeranz |
| 2025 | VTS | Chip Aging and Double Transition Faults. | Irith Pomeranz |
| 2025 | VTS | Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test Sequences. | Irith Pomeranz |
| 2025 | VTS | Timing-Verification Test Generation Targeting Small Delay Defects. | Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski |
| 2024 | ITC | Delay Monitoring Under Different PVT Corners for Test and Functional Operation. | Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2024 | ITC | Functionally-Possible Gate-Exhaustive Bridging Faults. | Irith Pomeranz |
| 2024 | VTS | A Storage Based LBIST Scheme for Logic Diagnosis. | Subashini Gopalsamy, Irith Pomeranz |
| 2024 | VTS | Test Compaction Using (k, 1)-Cycle Tests. | Irith Pomeranz |
| 2023 | ITC | Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines. | Irith Pomeranz |
| 2023 | VTS | Fully Deterministic Storage Based Logic Built-In Self-Test. | Subashini Gopalsamy, Irith Pomeranz |
| 2023 | VTS | Expanding a Pool of Functional Test Sequences to Support Test Compaction. | Irith Pomeranz |
| 2023 | VTS | Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs. | Irith Pomeranz |
| 2022 | ITC | Test Generation for an Iterative Design Flow with RTL Changes. | Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2022 | ITC | Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models. | Irith Pomeranz |
| 2022 | VTS | Fast Test Generation for Structurally Similar Circuits. | Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2021 | VTS | Compact Set of LFSR Seeds for Diagnostic Tests. | Irith Pomeranz |
| 2020 | IOLTS | Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests. | Irith Pomeranz |
| 2020 | IOLTS | Reduced Fault Coverage as a Target for Design Scaffolding Security. | Irith Pomeranz, Sandip Kundu |
| 2020 | ITC | Selecting Close-to-Functional Path Delay Faults for Test Generation. | Irith Pomeranz |
| 2020 | VTS | Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs. | Irith Pomeranz |
| 2020 | VTS | Non-Masking Non-Robust Tests for Path Delay Faults. | Irith Pomeranz |
| 2019 | DATE | Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. | Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman |
| 2019 | ITC | Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults. | Irith Pomeranz |
| 2019 | ITC | Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. | Irith Pomeranz |
| 2019 | VTS | Test Compaction Under Bounded Transparent-Scan. | Irith Pomeranz |
| 2019 | VTS | Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. | Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman |
| 2018 | ETS | Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests. | Irith Pomeranz |
| 2018 | ETS | Interconnect-aware tests to complement gate-exhaustive tests. | Irith Pomeranz, Srikanth Venkataraman |
| 2018 | ITC | On Close-to-Functional Test Sequences. | Irith Pomeranz |
| 2017 | DATE | A bridging fault model for line coverage in the presence of undetected transition faults. | Irith Pomeranz |
| 2017 | ITC | Selecting target bridging faults for uniform circuit coverage. | Irith Pomeranz |
| 2017 | ITC | POSTT: Path-oriented static test compaction for transition faults in scan circuits. | Irith Pomeranz |
| 2017 | ITC | Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. | Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen |
| 2017 | VTS | Fail data reduction for diagnosis of scan chain faults under transparent-scan. | Irith Pomeranz |
| 2017 | VTS | Using piecewise-functional broadside tests for functional broadside test compaction. | Irith Pomeranz |
| 2016 | VTS | Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. | Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman |
| 2016 | VTS | A convergent procedure for partially-reachable states. | Irith Pomeranz |
| 2015 | DAC | Generation of close-to-functional broadside tests with equal primary input vectors. | Irith Pomeranz |
| 2015 | ETS | On test program compaction. | Marco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz |
| 2015 | ISCA | FaultHound: value-locality-based soft-fault tolerance. | Nitin, Irith Pomeranz, T. N. Vijaykumar |
| 2015 | VTS | Improving the accuracy of defect diagnosis by considering reduced diagnostic information. | Irith Pomeranz |
| 2015 | VTS | Test vector omission with minimal sets of simulated faults. | Irith Pomeranz |
| 2015 | VTS | Test compaction by test cube merging for four-way bridging faults. | Irith Pomeranz |
| 2015 | VTS | A definition of the number of detections for faults with single tests in a compact scan-based test set. | Irith Pomeranz |
| 2014 | DATE | Test and non-test cubes for diagnostic test generation based on merging of test cubes. | Irith Pomeranz |
| 2014 | DATE | Substituting transition faults with path delay faults as a basic delay fault model. | Irith Pomeranz |
| 2014 | ETS | A distance-based test cube merging procedure for compatible and incompatible test cubes. | Irith Pomeranz |
| 2014 | VTS | Innovative practices session 10C: Advances in DFT and compression. | Rohit Kapur, Irith Pomeranz |
| 2014 | VTS | Fault simulation with test switching for static test compaction. | Irith Pomeranz |
| 2014 | VTS | On the use of multi-cycle tests for storage of two-cycle broadside tests. | Irith Pomeranz |
| 2013 | DATE | On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes. | Irith Pomeranz |
| 2013 | ETS | Generation of compact multi-cycle diagnostic test sets. | Irith Pomeranz |
| 2013 | VTS | Path selection based on static timing analysis considering input necessary assignments. | Bo Yao, Arani Sinha, Irith Pomeranz |
| 2012 | ETS | On the detection of path delay faults by functional broadside tests. | Irith Pomeranz |
| 2012 | VTS | Static test compaction for transition faults under the hazard-based detection conditions. | Irith Pomeranz |
| 2011 | ASPDAC | Fault diagnosis aware ATE assisted test response compaction. | J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker |
| 2011 | DAC | Diagnosis of transition fault clusters. | Irith Pomeranz |
| 2011 | DATE | Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. | Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker |
| 2011 | DATE | Built-in generation of functional broadside tests. | Irith Pomeranz |
| 2011 | DDECS | Max-Fill: A method to generate high quality delay tests. | Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz |
| 2011 | ETS | On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. | Irith Pomeranz |
| 2011 | PRDC | Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity. | Irith Pomeranz |
| 2011 | PRDC | Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults. | Irith Pomeranz |
| 2011 | VTS | Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. | Irith Pomeranz |
| 2011 | VTS | On clustering of undetectable transition faults in standard-scan circuits. | Irith Pomeranz |
| 2010 | ASPDAC | Functional and partially-functional skewed-load tests. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | DATE | Reducing the storage requirements of a test sequence by using a background vector. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | DATE | On reset based functional broadside tests. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | ETS | Input test data volume reduction based on test vector chains. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | IOLTS | Selecting state variables for improved on-line testability through output response comparison of identical circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | ITC | Multiple fault activation cycle tests for transistor stuck-open faults. | Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz |
| 2010 | VLSID | Output-Dependent Diagnostic Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | VLSID | Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | VTS | Defect diagnosis based on DFM guidelines. | Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman |
| 2010 | VTS | Forming multi-cycle tests for delay faults by concatenating broadside tests. | Irith Pomeranz, Sudhakar M. Reddy |
| 2010 | VTS | On multiple bridging faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2009 | ASPDAC | Dynamic test compaction for a random test generation procedure with input cube avoidance. | Irith Pomeranz, Sudhakar M. Reddy |
| 2009 | ASPDAC | Detectability of internal bridging faults in scan chains. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2009 | DATE | Selection of a fault model for fault diagnosis based on unique responses. | Irith Pomeranz, Sudhakar M. Reddy |
| 2009 | DATE | A scalable method for the generation of small test sets. | Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz |
| 2009 | ETS | Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2009 | VLSID | The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | ASPDAC | Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | ASPDAC | Test vector chains for increased targeted and untargeted fault coverage. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | DAC | On tests to detect via opens in digital CMOS circuits. | Sudhakar M. Reddy, Irith Pomeranz, Chen Liu |
| 2008 | DATE | A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | DATE | A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | ETS | Safe Fault Collapsing Based on Dominance Relations. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | IOLTS | An Enhanced Logic BIST Architecture for Online Testing. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2008 | ITC | Detection of Internal Stuck-open Faults in Scan Chains. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2008 | VLSID | Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | VLSID | Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | VLSID | On Common-Mode Skewed-Load and Broadside Tests. | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
| 2008 | VTS | Synthesis for Broadside Testability of Transition Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | VTS | Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. | Irith Pomeranz, Sudhakar M. Reddy |
| 2008 | VTS | On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
| 2007 | ASPDAC | Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz |
| 2007 | DATE | On test generation by input cube avoidance. | Irith Pomeranz, Sudhakar M. Reddy |
| 2007 | ETS | Diagnostic Test Generation Based on Subsets of Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2007 | ITC | Testing for systematic defects based on DFM guidelines. | Dongok Kim, M. Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau |
| 2007 | ITC | On the saturation of n-detection test sets with increased n. | Irith Pomeranz, Sudhakar M. Reddy |
| 2007 | VLSID | Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. | Irith Pomeranz, Sudhakar M. Reddy |
| 2007 | VLSID | Functional Broadside Tests with Different Levels of Reachability. | Irith Pomeranz, Sudhakar M. Reddy |
| 2007 | VLSID | Low Shift and Capture Power Scan Tests. | Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2007 | VTS | Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | DAC | A test pattern ordering algorithm for diagnosis with truncated fail data. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | DATE | Generation of broadside transition fault test sets that detect four-way bridging faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | DATE | Test compaction for transition faults under transparent-scan. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | ETS | A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. | Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz |
| 2006 | ETS | Fault Collapsing for Transition Faults Using Extended Transition Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | ETS | Enhancing Delay Fault Coverage through Low Power Segmented Scan. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi |
| 2006 | ICCAD | A delay fault model for at-speed fault simulation and test generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | IOLTS | A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. | Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz |
| 2006 | ITC | A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. | Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz |
| 2006 | ITC | Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | ITC | Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. | Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | VLSID | New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | VLSID | The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | VTS | A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | VTS | Dominance Based Analysis for Large Volume Production Fail Diagnosis. | Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy |
| 2006 | VTS | Scan Tests with Multiple Fault Activation Cycles for Delay Faults. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
| 2005 | DAC | N-detection under transparent-scan. | Irith Pomeranz |
| 2005 | DATE | Worst-Case and Average-Case Analysis of n-Detection Test Sets. | Irith Pomeranz, Sudhakar M. Reddy |
| 2005 | DATE | The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2005 | DATE | Defect Aware Test Patterns. | Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz |
| 2005 | ETS | A unified fault model and test generation procedure for interconnect opens and bridges. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker |
| 2005 | ETS | Using dummy bridging faults to define a reduced set of target faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2005 | ETS | Path-oriented transition fault test generation considering operating conditions. | Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
| 2005 | ICCD | A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. | Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz |
| 2005 | ISCAS | Battery-aware dynamic voltage scaling in multiprocessor embedded system. | Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi |
| 2005 | ITC | Methods for improving transition delay fault coverage using broadside tests. | Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz |
| 2005 | ITC | Forming N-detection test sets from one-detection test sets without test generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2005 | VLSID | Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. | Irith Pomeranz, Sudhakar M. Reddy |
| 2005 | VLSID | On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. | Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz |
| 2004 | DAC | On test generation for transition faults with minimized peak power dissipation. | Wei Li, Sudhakar M. Reddy, Irith Pomeranz |
| 2004 | DAC | On the generation of scan-based test sets with reachable states for testing under functional operation conditions. | Irith Pomeranz |
| 2004 | DAC | Scan-BIST based on transition probabilities. | Irith Pomeranz |
| 2004 | DATE | Level of Similarity: A Metric for Fault Collapsing. | Irith Pomeranz, Sudhakar M. Reddy |
| 2004 | DATE | Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri |
| 2004 | ICCD | On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. | Irith Pomeranz, Sudhakar M. Reddy |
| 2004 | ITC | Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy |
| 2004 | VLSID | On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. | Irith Pomeranz, Sudhakar M. Reddy |
| 2004 | VLSID | Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. | Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen |
| 2003 | DAC | A scan BIST generation method using a markov source and partial bit-fixing. | Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz |
| 2003 | DAC | On test data compression and n-detection test sets. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | DATE | A New Approach to Test Generation and Test Compaction for Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | DATE | Test Data Compression Based on Output Dependence. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | DATE | On the Characterization of Hard-to-Detect Bridging Faults. | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
| 2003 | ETS | On path selection for delay fault testing considering operating conditions [logic IC testing]. | Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
| 2003 | ICCAD | On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | ICCAD | On Compacting Test Response Data Containing Unknown Values. | Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer |
| 2003 | ICCD | Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz |
| 2003 | ICCD | A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz |
| 2003 | ICCD | Static Test Compaction for Multiple Full-Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | IOLTS | An Improved Markov Source Design for Scan BIST. | Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz |
| 2003 | ISCA | Transient-Fault Recovery for Chip Multiprocessors. | Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar |
| 2003 | ITC | On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. | Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
| 2003 | ITC | Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. | Irith Pomeranz |
| 2003 | ITC | On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. | Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz |
| 2003 | VLSID | Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | VLSID | GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. | Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz |
| 2003 | VTS | On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | VTS | A Test Interface for Built-In Test of Non-Isolated Scanned Cores. | Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian |
| 2003 | VTS | Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. | Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz |
| 2003 | VTS | SOC Test Scheduling Using Simulated Annealing. | Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang |
| 2002 | DAC | On output response compression in the presence of unknown output values. | Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy |
| 2002 | DATE | Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | DATE | Finding a Common Fault Response for Diagnosis during Silicon Debug. | Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy |
| 2002 | DATE | Fault Isolation Using Tests for Non-Isolated Blocks. | Irith Pomeranz, Yervant Zorian |
| 2002 | ETS | On selecting testable paths in scan designs. | Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
| 2002 | ICCAD | On undetectable faults in partial scan circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | ICCAD | Conflict driven techniques for improving deterministic test pattern generation. | Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
| 2002 | ICCD | A Low Power Pseudo-Random BIST Technique. | Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz |
| 2002 | ICCD | Don't-Care Identification on Specific Bits of Test Patterns. | Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | ICCD | On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. | Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | IOLTS | A Low Power Pseudo-Random BIST Technique. | Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz |
| 2002 | ISCA | Transient-Fault Recovery Using Simultaneous Multithreading. | T. N. Vijaykumar, Irith Pomeranz, Karl Cheng |
| 2002 | ITC | Pseudo Random Patterns Using Markov Sources for Scan BIST. | Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz |
| 2002 | ITC | On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. | Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita |
| 2002 | VLSID | A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | VLSID | Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. | Yun Shao, Irith Pomeranz, Sudhakar M. Reddy |
| 2002 | VTS | Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. | M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs |
| 2002 | VTS | On Test Data Volume Reduction for Multiple Scan Chain Designs. | Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz |
| 2001 | DAC | Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. | Irith Pomeranz |
| 2001 | DAC | An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | DATE | Sequence reordering to improve the levels of compaction achievable by static compaction procedures. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | DATE | Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | ICCAD | REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. | Chen Wang, Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | ICCD | COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | ICCD | A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | ITC | On static test compaction and test pattern ordering for scan designs. | Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | ITC | A method to enhance the fault coverage obtained by output response comparison of identical circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | ITC | On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | VLSID | On Improving Static Test Compaction for Sequential Circuits. | Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | VTS | Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. | M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana |
| 2001 | VTS | On the Use of Fault Dominance in n-Detection Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | DAC | On diagnosis of pattern-dependent delay faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | DATE | Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | DATE | Functional Test Generation for Full Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | DSN | Test-Point Insertion to Enhance Test Compaction for Scan Designs. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | ETS | On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | ICCAD | Improving the Proportion of At-Speed Tests in Scan BIST. | Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski |
| 2000 | ICCAD | Simulation Based Test Generation for Scan Designs. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | ICCD | Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | ICCD | On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | ITC | Selection of potentially testable path delay faults for test generation. | Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | ITC | On validating data hold times for flip-flops in sequential circuits. | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta |
| 2000 | PRDC | Fault diagnosis based on parameters of output responses. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | VLSID | Test Transformation to Improve Compaction by Statistical Encoding. | Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | VLSID | On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | VTS | SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. | Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | DAC | Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. | Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz |
| 1999 | DAC | Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | DATE | Full Scan Fault Coverage With Partial Scan. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ETS | On avoiding undetectable faults during test generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ICCAD | Techniques for improving the efficiency of sequential circuit test generation. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ICCAD | An approach for improving the levels of compaction achieved by vector omission. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ICCD | Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ITC | On achieving complete coverage of delay faults in full scan circuits using locally available lines. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | ITC | The effects of test compaction on fault diagnosis. | Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz |
| 1999 | VLSID | VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | VTS | Implication and Evaluation Techniques for Proving Fault Equivalence. | M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana |
| 1999 | VTS | A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. | Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | VTS | A Flexible Path Selection Procedure for Path Delay Fault Testing. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | VTS | On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | VTS | Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. | Irith Pomeranz, Yervant Zorian |
| 1999 | VTS | Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. | Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin |
| 1998 | DATE | Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. | Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | DATE | A Synthesis Procedure for Flexible Logic Functions. | Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | DATE | Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. | Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | ICCD | On finding undetectable and redundant faults in synchronous sequential circuits. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | ICCD | Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | ITC | A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. | Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VLSID | MIX: A Test Generation System for Synchronous Sequential Circuits. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VLSID | On Test Compaction Objectives for Combinational and Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VTS | On Removing Redundant Faults in Synchronous Sequential Circuits. | Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VTS | On Synchronizing Sequences and Test Sequence Partitioning. | Irith Pomeranz, Sudhakar M. Reddy |
| 1998 | VTS | Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | DAC | Fault Simulation under the Multiple Observation Time Approach using Backward Implications. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | DATE | On improving genetic optimization based test generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | DATE | On the use of reset to increase the testability of interconnected finite-state machines. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | ICCAD | Built-in test generation for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | ICCD | Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | VLSID | A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. | Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | VLSID | On the Detection of Reset Faults in Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | VLSID | On Full Reset as a Design-For-Testability Technique. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | VTS | EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | VTS | On n-detection test sequences for synchronous sequential circuits343. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | DAC | On Static Compaction of Test Sequences for Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | DATE | On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | ICCD | Fault Location Based on Circuit Partitioning. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | ITC | On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | ITC | Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. | Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li |
| 1996 | ITC | On Potential Fault Detection in Sequential Circuits. | Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz |
| 1996 | VLSID | On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | VTS | Synchronization of large sequential circuits by partial reset. | Yuan Lu, Irith Pomeranz |
| 1996 | VTS | On the effects of test compaction on defect coverage. | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
| 1996 | VTS | On minimizing the number of test points needed to achieve complete robust path delay fault testability. | Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz |
| 1995 | DAC | On Synthesis-for-Testability of Combinational Logic Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | ICCAD | Functional test generation for delay faults in combinational circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | ICCD | Test generation for multiple state-table faults in finite-state machines. | Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | ITC | Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. | Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | VLSID | MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. | Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | VTS | Compact test generation for bridging faults under I | Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara |
| 1994 | DAC | Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | DAC | On Improving Fault Diagnosis for Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | ICCAD | On testing delay faults in macro-based combinational circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | ICCAD | On error correction in macro-based circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | ITC | On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | VLSID | On Determining Symmetries in Inputs of Logic Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1994 | VTS | On compacting test sets by addition and removal of test vectors. | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy |
| 1994 | VTS | On identifying undetectable and redundant faults in synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | DAC | Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy |
| 1993 | DAC | Untitled record | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | DAC | NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. | Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri |
| 1993 | ICCAD | Test generation for path delay faults based on learning. | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | ICCAD | On diagnosis and correction of design errors. | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | ICCAD | Fault dictionary compression and equivalence class computation for sequential circuits. | Paul G. Ryan, W. Kent Fuchs, Irith Pomeranz |
| 1993 | ITC | A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | VLSID | On the Generation of Weights for Weighted Pseudo Random Testing. | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | VTS | Aliasing computation using fault simulation with fault dropping. | Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | DAC | State Assignment Using Input/Output Functions. | Irith Pomeranz, Kwang-Ting Cheng |
| 1992 | DAC | At-Speed Delay Testing of Synchronous Sequential Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | ICCAD | On the generation of small dictionaries for fault location. | Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | ICCAD | An efficient non-enumerative method to estimate path delay fault coverage. | Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | ICCAD | COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. | Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | ICPP | Effect of Communication in a Parallel Genetic Algorithm. | Venkataramana Kommu, Irith Pomeranz |
| 1992 | VLSID | 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. | Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | VTS | Generalization of independent faults for transition faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 1991 | DAC | On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. | Irith Pomeranz, Sudhakar M. Reddy |
| 1991 | ICCAD | Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. | Irith Pomeranz, Sudhakar M. Reddy |
| 1991 | ICCAD | Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. | Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy |
| 1991 | ITC | Achieving Complete Delay Fault Testability by Extra Inputs. | Irith Pomeranz, Sudhakar M. Reddy |
| 1991 | ITC | COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. | Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy |