Design of MoS2 based Inverter Circuits considering Interface Trap effect.
S. Sarath, Darshni Manekar, Rajendra P. Shukla, Chandan Yadav
Browse the full VLSID paper archive.
S. Sarath, Darshni Manekar, Rajendra P. Shukla, Chandan Yadav
Browse the full VLSID paper archive.