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Paper
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.
Hak-soo Yu
,
Jacob A. Abraham
Venue
National
VLSID
Year
2002
Proceedings
ASP-DAC/VLSI Design
DBLP record
conf/vlsid/YuA02 ↗
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