| 1999 | DAC | Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. | Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw |
| 1999 | VLSID | A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. | Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury |
| 1998 | DAC | Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. | Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden |
| 1998 | DAC | Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. | Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw |
| 1998 | DATE | CMOS Combinational Circuit Sizing by Stage-wise Tapering. | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |
| 1998 | ISLPED | Emerging power management tools for processor design. | David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards |
| 1997 | ICCAD | Library-less synthesis for static CMOS combinational logic circuits. | Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw |
| 1997 | ICCD | Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. | Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning |
| 1996 | DAC | iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. | Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang |
| 1994 | ICCAD | Fast timing simulation of transient faults in digital circuits. | Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel |
| 1994 | ICCAD | Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. | Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee |
| 1993 | DAC | Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. | Abhijit Dharchoudhury, Sung-Mo Kang |
| 1992 | DAC | An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. | Abhijit Dharchoudhury, Sung-Mo Kang |
| 1992 | VLSID | Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis. | Abhijit Dharchoudhury, S. M. Kang |