Abhishek Kumar Jain
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
5
Active years
2015–2023
Best venue rank
National
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | FCCM | Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. | Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde |
| 2020 | FPL | A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. | Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde |
| 2020 | ISCAS | High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. | Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain |
| 2018 | DATE | A time-multiplexed FPGA overlay with linear interconnect. | Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy |
| 2018 | FCCM | Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments. | Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale |
| 2016 | DASC | Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? | Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy |
| 2016 | DATE | Throughput oriented FPGA overlays using DSP blocks. | Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy |
| 2016 | FCCM | DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. | Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy |
| 2015 | FCCM | Efficient Overlay Architecture Based on DSP Blocks. | Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell |