| 2018 | ICISSP | Alignment-free Cancellable Template Generation for Fingerprint based Authentication. | Rumana Nazmul, Md. Rafiqul Islam, Ahsan Raja Chowdhury |
| 2015 | VLSID | Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis. | Sajib Kumar Mitra, Ahsan Raja Chowdhury |
| 2015 | VLSID | On the Analysis of Reversible Booth's Multiplier. | Jakia Sultana, Sajib Kumar Mitra, Ahsan Raja Chowdhury |
| 2014 | ICONIP | Reconstructing Gene Regulatory Network with Enhanced Particle Swarm Optimization. | Rezwana Sultana, Dilruba Showkat, Mohammad Samiullah, Ahsan Raja Chowdhury |
| 2013 | GECCO | Inferring large scale genetic networks with S-system model. | Ahsan Raja Chowdhury, Madhu Chetty, Xuan Vinh Nguyen |
| 2013 | ICONIP | On the Analysis of Time-Delayed Interactions in Genetic Network Using S-System Model. | Ahsan Raja Chowdhury, Madhu Chetty, Xuan Vinh Nguyen |
| 2013 | ICONIP | Reverse Engineering Genetic Networks with Time-Delayed S-System Model and Pearson Correlation Coefficient. | Ahsan Raja Chowdhury, Madhu Chetty, Xuan Vinh Nguyen |
| 2013 | VLSID | Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. | Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury |
| 2012 | CEC | Adaptive regulatory genes cardinality for reconstructing genetic networks. | Ahsan Raja Chowdhury, Madhu Chetty, Xuan Vinh Nguyen |
| 2012 | ICONIP | On the Reconstruction of Genetic Network from Partial Microarray Data. | Ahsan Raja Chowdhury, Madhu Chetty, Xuan Vinh Nguyen |
| 2012 | VLSID | Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis. | Sajib Kumar Mitra, Ahsan Raja Chowdhury |
| 2011 | CEC | An improved method to infer Gene Regulatory Network using S-System. | Ahsan Raja Chowdhury, Madhu Chetty |
| 2008 | VLSID | A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. | Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu |
| 2006 | VLSID | A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. | Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu |
| 2005 | VLSID | Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. | Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury |
| 2004 | ISCAS | A heuristic approach to synthesize Boolean functions using TANT network. | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury |
| 2004 | VLSID | Synthesis of Full-Adder Circuit Using Reversible Logic. | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury |
| 2003 | DSD | Reversible Logic Synthesis for Minimization of Full-Adder Circuit. | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury |