| 2010 | FPL | Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. | Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2009 | ARITH | Challenges in Automatic Optimization of Arithmetic Circuits. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | ASPDAC | Hybrid LZA: a near optimal implementation of the leading zero anticipator. | Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | ICCAD | Iterative layering: Optimizing arithmetic circuits by structuring the information flow. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | ASPDAC | Fast, quasi-optimal, and pipelined instruction-set extensions. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | DATE | Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2007 | ASPDAC | Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. | Ajay Kumar Verma, Paolo Ienne |
| 2007 | CASES | An optimistic and conservative register assignment heuristic for chordal graphs. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2007 | CASES | Rethinking custom ISE identification: a new processor-agnostic method. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2007 | DAC | Enhancing FPGA Performance for Arithmetic Circuits. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar |
| 2007 | DAC | Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2007 | DATE | Automatic synthesis of compressor trees: reevaluating large counters. | Ajay Kumar Verma, Paolo Ienne |
| 2007 | ICCAD | Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2006 | DAC | Towards the automatic exploration of arithmetic-circuit architectures. | Ajay Kumar Verma, Paolo Ienne |
| 2006 | DATE | Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. | Johann Groschdl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma |
| 2004 | ICCAD | Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. | Ajay Kumar Verma, Paolo Ienne |