| 2009 | CHES | A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. | Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh |
| 2009 | ISCAS | Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation. | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2009 | ISCAS | Compact and High-speed Hardware Architectures for Hash Function Tiger. | Akashi Satoh, Nicolas Sklavos |
| 2009 | WISA | Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. | Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh |
| 2008 | CHES | Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. | Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir |
| 2008 | CHES | High-Performance Concurrent Error Detection Scheme for AES Hardware. | Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki |
| 2008 | FPL | Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. | Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda |
| 2008 | FPL | Chosen-message SPA attacks against FPGA-based RSA hardware implementations. | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2008 | ICCD | Systematic design of high-radix Montgomery multipliers for RSA processors. | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2008 | ISCAS | Enhanced power analysis attack using chosen message against RSA hardware implementations. | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2008 | ISCAS | ASIC hardware implementations for 512-bit hash function Whirlpool. | Akashi Satoh |
| 2008 | ISCAS | High-performance ASIC implementations of the 128-bit block cipher CLEFIA. | Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2008 | IWSEC | Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. | Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda |
| 2008 | WISA | Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. | Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2007 | ISCAS | SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. | Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2007 | ISCAS | DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. | Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh |
| 2007 | ISCAS | High-Speed Parallel Hardware Architecture for Galois Counter Mode. | Akashi Satoh |
| 2007 | ISCAS | A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. | Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh |
| 2006 | CHES | High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. | Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh |
| 2006 | ISCAS | High-speed hardware architectures for authenticated encryption mode GCM. | Akashi Satoh |
| 2003 | CHES | Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. | Akashi Satoh, Sumio Morioka |
| 2002 | CHES | An Optimized S-Box Circuit Architecture for Low Power AES Design. | Sumio Morioka, Akashi Satoh |
| 2002 | ICCD | A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. | Sumio Morioka, Akashi Satoh |
| 2001 | ASIACRYPT | A Compact Rijndael Hardware Architecture with S-Box Optimization. | Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh |
| 1997 | ICCD | Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. | W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi |