Alejandro Valero
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
10
Active years
2009–2026
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISLPED | Exploiting Data Truncation for Lifetime Extension in ORB Accelerators. | Nicols Landeros Muoz, Alejandro Valero, Ruben Gran Tejero |
| 2024 | ICCD | Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage. | Yamilka Toca-Daz, Ruben Gran Tejero, Alejandro Valero |
| 2023 | DSD | On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators. | Yamilka Toca-Daz, Nicols Landeros Muoz, Ruben Gran Tejero, Alejandro Valero |
| 2022 | ICS | Fast-track cache: a huge racetrack memory L1 data cache. | Hugo Trrega, Alejandro Valero, Vicente Lorente, Salvador Petit, Julio Sahuquillo |
| 2019 | WCAE | Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. | Alejandro Valero, Daro Surez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustn Navarro-Torres, Adolfo Muoz, Joaqun Ezpeleta, Jos Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, Mara Villarroya-Gaud, Jess Alastruey-Bened, Enrique F. Torres, Pedro lvarez, Pablo Ibez, Vctor Vials |
| 2018 | EuroPar | Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache. | Francisco Candel, Salvador Petit, Alejandro Valero, Julio Sahuquillo |
| 2017 | SBAC-PAD | Exploiting Data Compression to Mitigate Aging in GPU Register Files. | Francisco Candel, Alejandro Valero, Salvador Petit, Daro Surez Gracia, Julio Sahuquillo |
| 2014 | HPCC | Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. | Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia, Julio Sahuquillo |
| 2013 | DATE | Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. | Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro Lpez, Jos Duato |
| 2013 | EuroPar | Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. | Vicente Lorente, Alejandro Valero, Ramon Canal |
| 2013 | ICS | Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches. | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Jos Duato |
| 2012 | ICCD | Analyzing the optimal ratio of SRAM banks in hybrid caches. | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro Lpez, Jos Duato |
| 2011 | SBAC-PAD | MRU-Tour-based Replacement Algorithms for Last-Level Caches. | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro Lpez, Jos Duato |
| 2009 | MICRO | An hybrid eDRAM/SRAM macrocell to implement first-level data caches. | Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro Lpez, Jos Duato |