Anant S. Kamath
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2010–2012
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ISCAS | A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS. | Anant S. Kamath, Biman Chattopadhyay |
| 2011 | ISCAS | Slew-rate controlled 800Mbps transmitter in 65nm CMOS. | Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty |
| 2011 | VLSID | A 1.8GHz Digital PLL in 65nm CMOS. | Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak |
| 2011 | VLSID | 42Gbps Source-Synchronous Transmitter in 45nm CMOS. | Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty |
| 2010 | ISCAS | A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. | Anant S. Kamath, Biman Chattopadhyay |