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Paper
A 1.8GHz Digital PLL in 65nm CMOS.
Biman Chattopadhyay
,
Anant S. Kamath
,
Gopalkrishna Nayak
Venue
National
VLSID
Year
2011
Proceedings
VLSI Design
DBLP record
conf/vlsid/ChattopadhyayKN11 ↗
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