Biman Chattopadhyay
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2010–2018
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | VLSID | A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. | Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta |
| 2016 | VLSID | A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. | Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak |
| 2012 | ISCAS | A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS. | Anant S. Kamath, Biman Chattopadhyay |
| 2011 | VLSID | A 1.8GHz Digital PLL in 65nm CMOS. | Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak |
| 2010 | ISCAS | A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. | Anant S. Kamath, Biman Chattopadhyay |