Gopalkrishna Nayak
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2011–2018
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | VLSID | A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. | Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta |
| 2016 | VLSID | A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. | Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak |
| 2011 | VLSID | A 1.8GHz Digital PLL in 65nm CMOS. | Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak |