| 2025 | COMPSAC | Privacy-Preserving Federated Learning for Household Characteristic Identification. | Erich Malan, Claudia De Vizia, Marco Castangia, Valentino Peluso, Andrea Calimera, Enrico Macii |
| 2025 | IJCNN | Gradient-Aware Participation for Energy Reduction in Federated Learning with Extreme Label Skew. | Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii |
| 2024 | ICCD | Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption. | Valentino Peluso, Erich Malan, Andrea Calimera, Enrico Macii |
| 2023 | ISLPED | Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. | Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii |
| 2022 | ISCAS | Privacy-preserving Social Distance Monitoring on Microcontrollers with Low-Resolution Infrared Sensors and CNNs. | Chen Xie, Francesco Daghero, Yukai Chen, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari |
| 2021 | DAC | On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage. | Antonio Cipolletta, Andrea Calimera |
| 2021 | DATE | Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks. | Antonio Cipolletta, Andrea Calimera |
| 2021 | ISLPED | ACME: An Energy-Efficient Approximate Bus Encoding for I | Chen Xie, Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2020 | CVPR | Enabling monocular depth perception at the very edge. | Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia |
| 2019 | DATE | Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. | Luca Mocerino, Valerio Tenace, Andrea Calimera |
| 2019 | DATE | Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. | Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia |
| 2019 | DATE | SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. | Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera |
| 2018 | DATE | All-digital embedded meters for on-line power estimation. | Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2018 | DATE | Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. | Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto |
| 2018 | ICCAD | Scalable-effort ConvNets for multilevel classification. | Valentino Peluso, Andrea Calimera |
| 2018 | ISCAS | Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. | Valentino Peluso, Andrea Calimera |
| 2018 | ISCAS | Multiplication by Inference using Classification Trees: A Case-Study Analysis. | Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera |
| 2018 | ISCAS | Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. | Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto |
| 2016 | ISCAS | Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2015 | DAC | One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2015 | ICCD | An automated design flow for approximate circuits based on reduced precision redundancy. | Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2015 | VLSID | Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs. | Felipe Lavratti, Letcia Maria Bolzani Poehls, Fabian Vargas, Andrea Calimera, Enrico Macii |
| 2014 | DATE | Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2014 | DSD | Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. | Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2013 | DAC | Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. | Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2013 | DATE | A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. | Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2012 | DATE | IR-drop analysis of graphene-based power distribution networks. | Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2012 | DATE | Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. | Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Richard Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo |
| 2012 | ISLPED | Energy-optimal caches with guaranteed lifetime. | Mirko Loghi, Haroon Mahmood, Andrea Calimera, Massimo Poncino, Enrico Macii |
| 2011 | DATE | Partitioned cache architectures for reduced NBTI-induced aging. | Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino |
| 2011 | DATE | Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. | Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino |
| 2010 | DATE | Post-placement temperature reduction techniques. | Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2010 | ISCAS | Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. | Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2010 | ISLPED | Dynamic indexing: concurrent leakage and aging optimization for caches. | Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino |
| 2009 | DATE | Enabling concurrent clock and power gating in an industrial design flow. | Letcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2009 | ISCAS | Placement-aware Clustering for Integrated Clock and Power Gating. | Letcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2009 | ISLPED | NBTI-aware power gating for concurrent leakage and aging optimization. | Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2008 | DATE | Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. | Andrea Calimera, Luca Benini, Enrico Macii |
| 2008 | DSD | Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. | Enrico Macii, Letcia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
| 2008 | ISCAS | On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2008 | ISLPED | Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. | Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino |
| 2007 | DATE | Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. | Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |