| 2025 | FPGA | Measuring the Minimum Power Requirement of FPGA Architectural Specifications. | Andy Gean Ye, Anas Razzaq |
| 2022 | FCCM | Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. | Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye |
| 2020 | FPL | Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. | Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye |
| 2017 | FPGA | Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only). | Andy Gean Ye, Karthik Ganesan |
| 2016 | FPL | An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures. | Farheen Fatima Khan, Andy Gean Ye |
| 2015 | ISCAS | Minimum jitter adaptive decision feedback equalizer for 4PAM serial links. | Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye |
| 2014 | ISCAS | A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links. | Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye |
| 2009 | FPGA | VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. | Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose |
| 2005 | FPGA | Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. | Andy Gean Ye, Jonathan Rose |
| 2005 | FPL | Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. | Andy Gean Ye, Jonathan Rose |
| 1999 | FPGA | Procedural Texture Mapping on FPGAs. | Andy Gean Ye, David M. Lewis |