Anees Ullah
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2013–2018
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | HPSR | Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays. | Pedro Reviriego, Salvatore Pontarelli, Anees Ullah, Ali Zahir, Giuseppe Bianchi |
| 2014 | FPL | Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. | Ernesto Snchez, Luca Sterpone, Anees Ullah |
| 2013 | ETS | An error-detection and self-repairing method for dynamically and partially reconfigurable systems. | Matteo Sonza Reorda, Luca Sterpone, Anees Ullah |