Anton Tsertov
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
4
Active years
2008–2019
Best venue rank
C
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ETS | Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks. | Aleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov |
| 2019 | ITC | Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. | Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Snchez, Giovanni Squillero, Anton Tsertov |
| 2016 | DDECS | FPGA-controlled PCBA power-on self-test using processor's debug features. | Boyang Du, Ernesto Snchez, Matteo Sonza Reorda, Julio Prez Acle, Anton Tsertov |
| 2016 | DDECS | High-level modeling and testing of multiple control faults in digital systems. | Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schlzel, Raimund Ubar |
| 2016 | ITC | A suite of IEEE 1687 benchmark networks. | Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath |
| 2015 | DDECS | New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. | Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar |
| 2011 | DSD | SoC and Board Modeling for Processor-Centric Board Testing. | Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze |
| 2008 | DDECS | Calculation of LFSR Seed and Polynomial Pair for BIST Applications. | Artur Jutman, Anton Tsertov, Raimund Ubar |