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Arani Sinha

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

27

Venues

5

Active years

1999–2026

Best venue rank

National

Where they publish

Papers

27 indexed papers, newest first.

YearVenueTitleAuthors
2026VTSInnovative Practices Session: Recent Approaches in Dealing with Silent Data Corruption.Harish Dattatraya Dixit, Arani Sinha, Nithya Jagannathan, David P. Lerner, Francesco Angione
2026VTSLate Breaking Results - Test Selection for In-Field Testing Using a Two-Dimensional Aging Space.Irith Pomeranz, Subashini Gopalsamy, Arani Sinha, Yonsang Cho
2025ITCEfficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance.Gowsika Dharmaraj, Abhijit Chatterjee, Adit D. Singh, Arani Sinha
2025VTSSpecial Session: Trustworthy Hardware-AI at the Cloud.Francesco Angione, Paolo Bernardi, Alberto Bosio, Harish Dattatraya Dixit, Salvatore Pappalardo, Annachiara Ruospo, Ernesto Snchez, Arani Sinha, Vittorio Turco
2024ITCFunctional State Extraction using Scan DFT.Ilya Wagner, Pankaj Pant, Arani Sinha
2024VTSInnovative Practices Track: Session 3 Test and Functional Safety Standards.Arani Sinha
2024VTSInnovative Practices Track: Session 4 AI Applications in Test.Arani Sinha, Stefano Di Carlo
2024VTSInnovative Practices Track: Session 2 Silent Data Corruption.Arani Sinha, Adit D. Singh
2023ITCMaximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure.Arani Sinha, Glenn Coln-Bonet, Michael Fahy, Pankaj Pant, Haijing Mao, Akhilesh Shukla
2022ITCMulti-die Parallel Test Fabric for Scalability and Pattern Reusability.Arani Sinha, Yonsang Cho, Jon Easter, Meizel V. Leiva Rojas
2022VTSInnovative Practices Track: Silent Data Errors.Arani Sinha
2022VTSInnovative Practices Track: Next Generation Test Standards.Arani Sinha
2021ETSSynergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction.Sandip Ray, Arani Sinha
2021VTSTwo Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2020ITCSAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2019DATEResynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines.Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman
2019ITCCharacterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee
2019VTSSilicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests.Ankit Shah, Raman Nayyar, Arani Sinha
2017ITCDFM-aware fault model and ATPG for intra-cell and inter-cell defects.Arani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz
2017VTSInnovative practices session 1C screening for layout sensitive defects.Arani Sinha, Nitin Chaudhary
2013VTSPath selection based on static timing analysis considering input necessary assignments.Bo Yao, Arani Sinha, Irith Pomeranz
2011VTSA Novel mechanism for speed characterization during delay test.Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou
2011VTSThe buck stops with wafer test: Dream or reality?Suriyaprakash Natarajan, Arani Sinha
2011VTSThe bang for the buck with resiliency: Yield or field?Arani Sinha, Suriyaprakash Natarajan
2010VTSSpecial session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?Arani Sinha
2009VTSPanel: Analog Characterization and Test: The Long Road to Realization.Arani Sinha, Amitava Majumdar, Vasu Ganti
1999ICCADValidation and test generation for oscillatory noise in VLSI interconnects.Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer