| 2010 | DSD | Optimising Self-Timed FPGA Circuits. | Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume |
| 2008 | DDECS | A Partial Scan Based Test Generation for Asynchronous Circuits. | Dilip P. Vasudevan, Aristides Efthymiou |
| 2007 | AINA | Synthetic Trace-Driven Simulation of Cache Memory. | Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou |
| 2007 | DDECS | Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. | Aristides Efthymiou |
| 2005 | IOLTS | Fast, Parallel Two-Rail Code Checker with Enhanced Testability. | Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou |
| 2004 | DATE | Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. | Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards |
| 2002 | ICCD | Adaptive Pipeline Depth Control for Processor Power-Management. | Aristides Efthymiou, Jim D. Garside |
| 2002 | ISLPED | An adaptive serial-parallel CAM architecture for low-power cache blocks. | Aristides Efthymiou, Jim D. Garside |
| 1995 | SIGCOMM | Pipelined Memory Shared Buffer for VLSI Switches. | Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou |