| 2024 | DSN | Optimizing Large-Scale Fault Injection Experiments through Martingale Hypothesis: A Systematic Approach for Reliability Assessment of Safety-Critical Systems. | Saurabh Hukerikar, Atieh Lotfi, Yanxiang Huang, Jason Campbell, Nirmal R. Saxena |
| 2022 | ITC | Error Model (EM) - A New Way of Doing Fault Simulation. | Nirmal R. Saxena, Atieh Lotfi |
| 2019 | DATE | Accelerating Local Binary Pattern Networks with Software-Programmable FPGAs. | Jeng-Hau Lin, Atieh Lotfi, Vahideh Akhlaghi, Zhuowen Tu, Rajesh K. Gupta |
| 2019 | ITC | Resiliency of automotive object detection networks on GPU architectures. | Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang |
| 2018 | DSN | Low Overhead Tag Error Mitigation for GPU Architectures. | Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani |
| 2017 | FPGA | RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only). | Atieh Lotfi, Rajesh K. Gupta |
| 2017 | ICCD | ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis. | Atieh Lotfi, Rajesh K. Gupta |
| 2016 | DATE | Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration. | Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta |
| 2012 | IOLTS | Architectural vulnerability aware checkpoint placement in a multicore processor. | Atieh Lotfi, Arash Bayat, Saeed Safari |