| 2025 | ASPDAC | Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis. | Md. Imtiaz Rashid, Benjamin Carrin Schfer |
| 2025 | ASPDAC | Efficient and Secure Cloud-based Split Logic Synthesis. | Chaitali Sathe, Yiorgos Makris, Benjamin Carrin Schfer |
| 2025 | ASPDAC | HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs. | Qilin Si, Benjamin Carrin Schfer |
| 2025 | DAC | ADVISOR: Approximate Computing-frienDly High-LeVel Synthesis DesIgn Space ExplORer. | Baharealsadat Parchamdar, Benjamin Carrin Schfer |
| 2024 | DAC | Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue. | Baharealsadat Parchamdar, Benjamin Carrin Schfer |
| 2023 | ISCAS | CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis. | M. Imtiaz Rashid, Amir H. Torabi, Benjamin Carrin Schfer |
| 2022 | ASPDAC | Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS. | M. Imtiaz Rashid, Benjamin Carrin Schfer |
| 2022 | ASPDAC | Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling. | Benjamin Carrin Schfer |
| 2022 | ISCAS | Modernizing Hardware Circuits through High-Level Synthesis. | Md. Imtiaz Rashid, Qilin Si, Benjamin Carrin Schfer |
| 2022 | ISLPED | Predictive Model Attack for Embedded FPGA Logic Locking. | Prattay Chowdhury, Chaitali Sathe, Benjamin Carrin Schfer |
| 2021 | ASPDAC | Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures. | Jianqi Chen, Benjamin Carrin Schfer |
| 2021 | DAC | Enabling the Design of Behavioral Systems-on-Chip. | Santosh Shetty, Benjamin Carrin Schfer |
| 2021 | DATE | Watermarking of Behavioral IPs: A Practical Approach. | Jianqi Chen, Benjamin Carrin Schfer |
| 2021 | DATE | Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions. | Zi Wang, Benjamin Carrin Schfer |
| 2021 | ICCD | Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing. | Prattay Chowdhury, Benjamin Carrin Schfer |
| 2021 | ICCD | Functional Locking through Omission: From HLS to Obfuscated Design. | Zi Wang, Shayan Omais Mohammed, Yiorgos Makris, Benjamin Carrin Schfer |
| 2021 | ISCAS | Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation. | Yiheng Gao, Benjamin Carrin Schfer |
| 2021 | ISCAS | Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing. | Zhiqi Zhu, Benjamin Carrin Schfer |
| 2021 | ISLPED | BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs. | Prattay Chowdhury, Benjamin Carrin Schfer |
| 2021 | VLSID | Efficient Hierarchical Post-Silicon Validation and Debug. | Pandy Kalimuthu, Kanad Basu, Benjamin Carrin Schfer |
| 2020 | DAC | DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. | Jianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrin Schfer |
| 2020 | DAC | Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration. | Zi Wang, Benjamin Carrin Schfer |
| 2020 | DATE | An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. | Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrin Schfer, Carl Sechen |
| 2020 | DATE | Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization. | Zi Wang, Jianqi Chen, Benjamin Carrin Schfer |
| 2020 | DATE | On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations. | Siyuan Xu, Benjamin Carrin Schfer |
| 2020 | ICCD | Bespoke Behavioral Processors. | Rohit Sreekumar, Prattay Chowdhury, Benjamin Carrin Schfer |
| 2020 | ISCAS | Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis. | Zhiqi Zhu, Benjamin Carrin Schfer |
| 2019 | DAC | Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration. | Shuangnan Liu, Francis C. M. Lau, Benjamin Carrin Schfer |
| 2019 | DATE | Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. | Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrin Schfer, Carl Sechen, Yiorgos Makris |
| 2019 | DATE | Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis. | Farah Naz Taher, Matthew Joslin, Anjana Balachandran, Zhiqi Zhu, Benjamin Carrin Schfer |
| 2019 | DATE | Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis. | Zi Wang, Benjamin Carrin Schfer |
| 2019 | FCCM | Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures. | Maheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran, Benjamin Carrin Schfer |
| 2019 | ICCAD | Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models. | Siyuan Xu, Benjamin Carrin Schfer |
| 2019 | ICCD | Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation. | Jianqi Chen, Benjamin Carrin Schfer |
| 2019 | ICCD | Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI Design. | Jianqi Chen, Benjamin Carrin Schfer |
| 2019 | ICCD | Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure. | Farah Naz Taher, Anjana Balachandran, Benjamin Carrin Schfer |
| 2019 | ICCD | Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations. | Siyuan Xu, Benjamin Carrin Schfer |
| 2019 | ISCAS | Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration. | Anushree Mahapatra, Benjamin Carrin Schfer |
| 2018 | DAC | A machine learning based hard fault recuperation model for approximate hardware accelerators. | Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrin Schfer |
| 2018 | ICCD | Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles. | Siyuan Xu, Benjamin Carrin Schfer |
| 2018 | ICCD | DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures. | Siyuan Xu, Benjamin Carrin Schfer |
| 2018 | IOLTS | Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis. | Farah Naz Taher, Mostafa Kishani, Benjamin Carrin Schfer |
| 2018 | PRDC | Control Flow Checking Optimization Based on Regular Patterns Analysis. | Zhiqi Zhu, Joseph Callenes-Sloan, Benjamin Carrin Schfer |
| 2017 | DSD | Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study. | Benjamin Carrin Schfer, David Aledo, Flix Moreno |
| 2017 | FPL | Learning-based interconnect-aware dataflow accelerator optimization. | Shuangnan Liu, Benjamin Carrin Schfer |
| 2017 | ICCD | Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads. | Siyuan Xu, Benjamin Carrin Schfer |
| 2017 | ICCD | Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration. | Siyuan Xu, Benjamin Carrin Schfer, Yidi Liu |
| 2016 | ASPDAC | Optimization of behavioral IPs in multi-processor system-on-chips. | Yidi Liu, Benjamin Carrin Schfer |
| 2016 | FPL | Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. | Dong Liu, Benjamin Carrin Schfer |
| 2015 | FPL | Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs. | Xiaotong Li, Benjamin Carrin Schfer |
| 2014 | ASPDAC | Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. | Benjamin Carrin Schfer |
| 2010 | ASPDAC | Design of complex image processing systems in ESL. | Benjamin Carrin Schfer, Ashish Trambadia, Kazutoshi Wakabayashi |
| 2010 | ISLPED | Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. | Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrin Schfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum |
| 2007 | RTCSA | Temperature-Aware Compilation for VLIWProcessors. | Benjamin Carrin Schfer, Yongho Lee, Taewhan Kim |
| 2002 | FCCM | Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing. | Benjamin Carrin Schfer, Steven F. Quigley, Andrew H. C. Chan |
| 2002 | FPL | Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform. | Benjamin Carrin Schfer, Steven F. Quigley, Andrew H. C. Chan |
| 2001 | FPL | Evaluation of an FPGA Implementation of the Discrete Element Method. | Benjamin Carrin Schfer, Steven F. Quigley, Andrew H. C. Chan |