Bharadwaj S. Amrutur
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
5
Active years
2006–2025
Best venue rank
National
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | COMSNETS | Physical Resource block Allocation in Private 5G Network for handoff Free operations. | Alok Mathur, Bharadwaj S. Amrutur |
| 2022 | COMSNETS | Tele-driving an electric vehicle over a private LTE network. | Ashish Joglekar, Alok Rawat, Ashwin Gerard Colaco, Aswin Prasad I S, Praphulla Ranjan, Raghava Doreswamy, Rajat Chopra, Bharadwaj S. Amrutur, Bharath Govindraju, Fashid Rahman, Himanshu Tyagi, Naveen Arulselvan, Preetam Patil, S. V. R. Anand, Vishal Sevani |
| 2020 | COMSNETS | CORNET: A Co-Simulation Middleware for Robot Networks. | Srikrishna Acharya, Bharadwaj S. Amrutur, Yogesh Simmhan, Aditya Gopalan, Parimal Parag, Himanshu Tyagi |
| 2010 | ISLPED | In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits. | Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur |
| 2008 | IOLTS | False Error Study of On-line Soft Error Detection Mechanisms. | M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji |
| 2008 | ISLPED | Optimal power and noise allocation for analog and digital sections of a low power radio receiver. | Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat |
| 2008 | VLSID | Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. | S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur |
| 2008 | VLSID | A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. | Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur |
| 2007 | VLSID | Modified Stability Checking for On-line Error Detection. | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji |
| 2006 | ICS | A scalable low power issue queue for large instruction window processors. | Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan |