| 2008 | ISCAS | ROM based logic (RBL) design: High-performance and low-power adders. | Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima |
| 2006 | DATE | Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. | Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy |
| 2006 | DATE | Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. | Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy |
| 2005 | DATE | Statistical Timing Analysis using Levelized Covariance Propagation. | Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy |
| 2004 | ASPDAC | Adaptive supply voltage technique for low swing interconnects. | Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy |
| 2004 | DAC | Novel sizing algorithm for yield improvement under process variation in nanometer technology. | Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy |
| 2004 | IOLTS | A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. | Amit Agarwal, Bipul Chandra Paul, Kaushik Roy |
| 2004 | ISLPED | Device optimization for ultra-low power digital sub-threshold operation. | Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy |
| 2004 | ITC | Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. | Bipul Chandra Paul, Cassondra Neau, Kaushik Roy |
| 2002 | ITC | Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. | Bipul Chandra Paul, Kaushik Roy |
| 2002 | VLSID | Dynamic Noise Analysis with Capacitive and Inductive Coupling. | Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy |
| 2001 | VLSID | Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. | Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul |
| 2000 | ISLPED | Robust ultra-low power sub-threshold DTMOS logic. | Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul |