| 2004 | ITC | A Hierarchical DFT Architecture for Chip, Board and System Test/Debug. | Charles Njinda |
| 1997 | DAC | Efficient Testing of Clock Regenerator Circuits in Scan Designs. | Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh |
| 1997 | ITC | How Seriously Do You Take Your Possible-Detect Faults? | Rajesh Raina, Charles Njinda, Robert F. Molyneaux |
| 1995 | ITC | Performance Driven BIST Technique for Random Logic. | Charles Njinda, Neeraj Kaul |
| 1994 | DAC | Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. | Ishwar Parulkar, Melvin A. Breuer, Charles Njinda |
| 1992 | DAC | SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. | Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer |
| 1992 | ITC | Optimal Sequencing of Scan Registers. | Sridhar Narayanan, Charles Njinda, Melvin A. Breuer |
| 1991 | ICCAD | A Systematic Approach for Designing Testable VLSI Circuits. | Sen-Pin Lin, Charles Njinda, Melvin A. Breuer |
| 1991 | ICCAD | Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. | Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer |
| 1991 | VTS | A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. | Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer |