| 2011 | VTS | Design for Bit Error Rate estimation of high speed serial links. | Ujjwal Guin, Chen-Huan Chiang |
| 2008 | ITC | A New Language Approach for IJTAG. | Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook |
| 2008 | ITC | Problems Using Boundary-Scan for Memory Cluster Tests. | Bradford G. Van Treuren, Chen-Huan Chiang, Kenneth Honaker |
| 2007 | ITC | A practical approach to comprehensive system test & debug using boundary scan based test architecture. | Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren |
| 2004 | ITC | Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. | Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung |
| 2002 | ITC | A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. | Tapan J. Chakraborty, Chen-Huan Chiang |
| 2000 | ITC | End-to-end testing for boards and systems using boundary scan. | Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace |
| 1997 | ICCAD | BIST TPG for faults in system backplanes. | Chen-Huan Chiang, Sandeep K. Gupta |
| 1997 | VTS | BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. | Chen-Huan Chiang, Sandeep K. Gupta |
| 1994 | ICCAD | Random pattern testable logic synthesis. | Chen-Huan Chiang, Sandeep K. Gupta |