Chih-Sheng Hou
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2010–2016
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ITC | A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. | Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
| 2013 | VTS | Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs. | Chih-Sheng Hou, Jin-Fu Li |
| 2013 | VTS | A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. | Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
| 2012 | ETS | Disturbance fault testing on various NAND flash memories. | Chih-Sheng Hou, Jin-Fu Li |
| 2010 | VTS | Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. | Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li |