Skip to content

Ching-Yuan Chen

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

6

Active years

2019–2023

Best venue rank

A*

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2023ETSAttacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors.Ching-Yuan Chen, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty
2023VTSFunctional Test Generation for AI Accelerators using Bayesian OptimizationArjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Krishnendu Chakrabarty
2021DACPruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators.Ching-Yuan Chen, Krishnendu Chakrabarty
2021DATEEfficient Identification of Critical Faults in Memristor Crossbars for Deep Neural Networks.Ching-Yuan Chen, Krishnendu Chakrabarty
2021ITCEfficient Fault-Criticality Analysis for AI Accelerators using a Neural TwinArjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Siddarth Madala, Abhishek Kumar Dubey, Krishnendu Chakrabarty
2021ITCOn-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums.Ching-Yuan Chen, Krishnendu Chakrabarty
2020ETSFunctional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model.Ching-Yuan Chen, Ching-Hong Cheng, Jiun-Lang Huang, Krishnendu Chakrabarty
2019DDECSTestability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime.Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang