| 2026 | FCCM | A Hybrid Ising FPGA-COBI Architecture with Hardware-Based Problem Decomposition. | Ruihong Yin, Yue Zheng, Chaohui Li, Ahmet Efe, Abhimanyu Kumar, Ziqing Zeng, Ulya R. Karpuzcu, Sachin S. Sapatnekar, Chris H. Kim |
| 2026 | ISCA | SATIC: An Optimizing Ising Compiler for SAT(isfiability). | Ahmet Efe, Hsrev Cilasun, Abhimanyu Kumar, Nafisa Sadaf Prova, Ziqing Zeng, Tahmida Islam, Ruihong Yin, Chaohui Li, Peter Kreye, Chris H. Kim, Sachin S. Sapatnekar, Ulya R. Karpuzcu |
| 2018 | ASPDAC | Effect of aging on linear and nonlinear MUX PUFs by statistical modeling. | Anoop Koyily, Satya Venkata Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi |
| 2018 | ISCAS | BiometricNet: Deep Learning based Biometric Identification using Wrist-Worn PPG. | Luke R. Everson, Dwaipayan Biswas, Madhuri Panwar, Dimitrios Rodopoulos, Amit Acharyya, Chris H. Kim, Chris Van Hoof, Mario Konijnenburg, Nick Van Helleputte |
| 2018 | ISCAS | Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference. | Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi |
| 2018 | ISCAS | A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC. | Qianying Tang, Won Ho Choi, Luke R. Everson, Keshab K. Parhi, Chris H. Kim |
| 2017 | ACSSC | Functional encryption of integrated circuits by key-based hybrid obfuscation. | Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi |
| 2017 | DAC | A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. | Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami |
| 2017 | DAC | Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements. | Chen Zhou, Keshab K. Parhi, Chris H. Kim |
| 2017 | DATE | Advanced spintronic memory and logic for non-volatile processors. | Robert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jianping Wang |
| 2017 | ISCAS | Hierarchical functional obfuscation of integratec circuits using a mode-based approach. | Sandhya Koteshwara, Chris H. Kim, Keshab K. Parhi |
| 2017 | ISCAS | An entropy test for determining whether a MUX PUF is linear or nonlinear. | Anoop Koyily, Chen Zhou, Chris H. Kim, Keshab K. Parhi |
| 2017 | ISCAS | A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology. | Somnath Kundu, Chris H. Kim |
| 2017 | ISLPED | A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function. | Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi, Chris H. Kim |
| 2016 | DATE | Estimating delay differences of arbiter PUFs using silicon data. | S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi |
| 2016 | ISLPED | Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs. | Chen Zhou, Saroj Satapathy, Yingjie Lao, Keshab K. Parhi, Chris H. Kim |
| 2015 | ISCAS | Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR). | Rahul Parhi, Chris H. Kim, Keshab K. Parhi |
| 2014 | DATE | Improving STT-MRAM density through multibit error correction. | Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar |
| 2014 | VLSID | Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations. | Ayan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim |
| 2012 | ICCAD | Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. | Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar |
| 2012 | ISCAS | Design of ring oscillator structures for measuring isolated NBTI and PBTI. | Tony T. Kim, Pong-Fei Lu, Chris H. Kim |
| 2010 | ISCAS | Logic-compatible embedded DRAM design for memory intensive low power systems. | Ki Chul Chun, Pulkit Jain, Chris H. Kim |
| 2010 | ISLPED | Variation aware performance analysis of gain cell embedded DRAMs. | Wei Zhang, Ki Chul Chun, Chris H. Kim |
| 2009 | ASPDAC | Adaptive techniques for overcoming performance degradation due to aging in digital circuits. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2009 | ISLPED | A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. | Ki Chul Chun, Pulkit Jain, Chris H. Kim |
| 2008 | ISCAS | Circuit techniques for ultra-low power subthreshold SRAMs. | Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim |
| 2008 | ISLPED | A multi-story power delivery technique for 3D integrated circuits. | Pulkit Jain, Tony Tae-Hyoung Kim, John Keane, Chris H. Kim |
| 2008 | ISLPED | Enhancing | Dong Jiao, Jie Gu, Pulkit Jain, Chris H. Kim |
| 2007 | DAC | Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. | Jie Gu, Sachin S. Sapatnekar, Chris H. Kim |
| 2007 | DAC | NBTI-Aware Synthesis of Digital Circuits. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2007 | ISLPED | Sleep transistor sizing and control for resonant supply noise damping. | Jie Gu, Hanyong Eom, Chris H. Kim |
| 2007 | ISLPED | An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. | John Keane, Tony Tae-Hyoung Kim, Chris H. Kim |
| 2006 | ASPDAC | Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2006 | DAC | Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. | John Keane, Hanyong Eom, Tony Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim |
| 2006 | ICCAD | An analytical model for negative bias temperature instability. | Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar |
| 2006 | ISLPED | Modeling and analysis of leakage induced damping effect in low voltage LSIs. | Jie Gu, John Keane, Chris H. Kim |
| 2006 | ISLPED | A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting. | Jonggab Kil, Jie Gu, Chris H. Kim |
| 2006 | ISLPED | Utilizing reverse short channel effect for optimal subthreshold circuit design. | Tony Tae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim |
| 2005 | IOLTS | Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. | Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy |
| 2005 | ISLPED | Multi-story power delivery for supply noise reduction and low voltage operation. | Jie Gu, Chris H. Kim |
| 2004 | DAC | Leakage in nano-scale technologies: mechanisms, impact and design considerations. | Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy |
| 2004 | ISLPED | Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. | Hari Ananthan, Chris H. Kim, Kaushik Roy |
| 2003 | ISLPED | A forward body-biased low-leakage SRAM cache: device and architecture considerations. | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy |
| 2002 | DATE | Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. | Chris H. Kim, Kaushik Roy |
| 2002 | ISLPED | Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. | Chris H. Kim, Kaushik Roy |