| 2020 | VTS | Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. | Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng |
| 2013 | DATE | Co-synthesis of data paths and clock control paths for minimum-period clock gating. | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
| 2012 | ASPDAC | Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
| 2012 | ISCAS | A formal approach to slack-driven high-level synthesis. | Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng |
| 2009 | ASPDAC | Timing driven power gating in high-level synthesis. | Shih-Hsu Huang, Chun-Hua Cheng |
| 2009 | ISCAS | Surge Current Minimization in High-level Synthesis. | Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang |
| 2007 | DAC | Clock Period Minimization with Minimum Delay Insertion. | Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh |
| 2007 | EUC | Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. | Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng |
| 2006 | DAC | Register binding for clock period minimization. | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
| 2005 | ISCAS | A formal approach to the slack driven scheduling problem in high-level synthesis. | Shih-Hsu Huang, Chun-Hua Cheng |