Chun-Yao Wang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
48
Venues
9
Active years
2001–2026
Best venue rank
A*
Where they publish
Papers
48 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Learning to Approximate: Circuit Learning and Deep Reinforcement Learning for Approximate Logic Synthesis with an Error Rate Guarantee. | Chi-Wei Chen, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Jian-Meng Yang, Chun-Yao Wang |
| 2026 | DATE | A Mathematical Exploration to Equivalence Checking of Quantum Circuits. | You-Cheng Lin, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Chia-Chieh Chu, Chun-Yao Wang |
| 2025 | DAC | Real-Time Dynamic IR-drop Prediction for IR ECO. | Yu-Che Lee, Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Jia-Wei Lin, Hsun-Wei Pao, Yung-Chih Chen, Yi-Ting Li, Wuqian Tang, Shih-Chieh Chang, Chun-Yao Wang |
| 2025 | DATE | Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration. | Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Peng-Wen Chen, Po-Yu Chen, Hao-Yun Chen, Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Chang |
| 2024 | ASPDAC | LOOPLock 3.0: A Robust Cyclic Logic Locking Approach. | Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, Chun-Yao Wang |
| 2024 | DATE | A Hybrid Approach to Reverse Engineering on Combinational Circuits. | Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang |
| 2023 | ASPDAC | Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee. | Chun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang |
| 2023 | ASPDAC | A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli. | Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang |
| 2023 | ICCAD | Invited Paper: Overview of 2023 CAD Contest at ICCAD. | Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang |
| 2022 | ICCAD | Overview of 2022 CAD Contest at ICCAD. | Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato |
| 2022 | ICCAD | An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0. | Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang |
| 2021 | ASPDAC | A General Equivalence Checking Framework for Multivalued Logic. | Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, Chun-Yao Wang |
| 2021 | ASPDAC | An Efficient Approximate Node Merging with an Error Rate Guarantee. | Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang |
| 2021 | ICCAD | Overview of 2021 CAD Contest at ICCAD. | Tsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato |
| 2020 | DATE | A Convolutional Result Sharing Approach for Binarized Neural Network Inference. | Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, Chun-Yao Wang |
| 2018 | DATE | Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. | Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang |
| 2018 | DATE | Logic optimization with considering boolean relations. | Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang |
| 2017 | ASPDAC | Majority logic circuits optimisation by node merging. | Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, Chia-Cheng Wu |
| 2016 | ASPDAC | MajorSat: A SAT solver to majority logic. | Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang |
| 2015 | ASPDAC | A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. | Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan |
| 2015 | DATE | Using structural relations for checking combinationality of cyclic circuits. | Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang |
| 2015 | ICCD | CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. | Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen |
| 2014 | DATE | Rewiring for threshold logic circuit minimization. | Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang |
| 2014 | DATE | Width minimization in the Single-Electron Transistor array synthesis. | Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan |
| 2014 | ICCAD | BDD-based synthesis of reconfigurable single-electron transistor arrays. | Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang, Weikang Qian |
| 2014 | IJCNN | Alzheimer's disease classification based on gait information. | Wei-Hsin Wang, Yu-Liang Hsu, Ming-Chyi Pai, Cheng-Hsiung Wang, Chun-Yao Wang, Chien-Wen Lin, Hao-Li Wu, Pau-Choo Chung |
| 2013 | DATE | On reconfigurable single-electron transistor arrays synthesis using reordering techniques. | Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan |
| 2013 | ICCAD | Sensitization criterion for threshold logic circuits and its application. | Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen |
| 2013 | ISCAS | Pattern generation for Mutation Analysis using Genetic Algorithms. | Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen |
| 2012 | DATE | A probabilistic analysis method for functional qualification under Mutation Analysis. | Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen |
| 2012 | ISCAS | Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer. | Pau-Choo Chung, Yu-Liang Hsu, Chun-Yao Wang, Chien-Wen Lin, Jeen-Shing Wang, Ming-Chyi Pai |
| 2011 | DAC | Automated mapping for reconfigurable single-electron transistor arrays. | Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan |
| 2011 | ICCAD | On rewiring and simplification for canonicity in threshold logic circuits. | Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang |
| 2010 | DAC | Node addition and removal in the presence of don't cares. | Yung-Chih Chen, Chun-Yao Wang |
| 2010 | ISPA | Distributed Transactions for Semantic Web Workflows - Overcoming the CAP Limitations on Virtual Organizations. | Daniel J. Buehrer, Chun-Yao Wang |
| 2010 | ISPA | The Cadabia Cloud. | Daniel J. Buehrer, Chun-Yao Wang, Li-Ren Chien |
| 2009 | ASPDAC | Dependent latch identification in the reachable state space. | Chen-Hsuan Lin, Chun-Yao Wang |
| 2009 | DATE | Rewiring using IRredundancy Removal and Addition. | Chun-Chi Lin, Chun-Yao Wang |
| 2009 | ICCAD | Fast detection of node mergers using logic implications. | Yung-Chih Chen, Chun-Yao Wang |
| 2007 | ASPDAC | Synthesis of Reversible Sequential Elements. | Min-Lun Chuang, Chun-Yao Wang |
| 2007 | ASPDAC | Recognition of Fanout-free Functions. | Tsung-Lin Lee, Chun-Yao Wang |
| 2006 | ASPDAC | High level equivalence symmetric input identification. | Ming-Hong Su, Chun-Yao Wang |
| 2005 | ICCD | An Improved Approach for AlternativeWires Identi.cation. | Yung-Chih Chen, Chun-Yao Wang |
| 2004 | ICCD | Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. | Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou |
| 2004 | ITC | Verification on Port Connections. | Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang |
| 2003 | ASPDAC | An automatic interconnection rectification technique for SoC design integration. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
| 2003 | ISCAS | SoC design integration by using automatic interconnection rectification. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |
| 2001 | ISCAS | An AVPG for SOC design verification with port order fault model. | Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou |