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Claudia Feregrino

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

4

Venues

3

Active years

1999–2006

Best venue rank

B

Where they publish

Papers

4 indexed papers, newest first.

YearVenueTitleAuthors
2006CIARPOn the Design and Implementation of a High Performance Configurable Architecture for Testor Identification.Ren Cumplido, Jess Ariel Carrasco-Ochoa, Claudia Feregrino
2001FPLX-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor.Jos Luis Nez, Claudia Feregrino, Simon R. Jones, Stephen Bateman
2001FPLFPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding.Riad Stefo, Jos Luis Nez, Claudia Feregrino, Sudipta Mahapatra, Simon R. Jones
1999FPGAThe X-MatchLITE FPGA-Based Data Compressor.Jos Luis Nez, Claudia Feregrino, Stephen Bateman, Simon R. Jones