Cong Hao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
40
Venues
17
Active years
2013–2026
Best venue rank
A*
Where they publish
Papers
40 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCA | Omelet: A Packaging-Aware Hierarchical Interconnect Simulator for 2.5D/3D Chiplet Architectures. | Jiho Kim, Danish Baig, Faaiq Waqar, Ashita Victor, Shimeng Yu, Muhannad S. Bakir, Cong Hao |
| 2026 | ICS | COMETS: Cost-effective Multi-node Efficient Training System with Memory Pooling and Sharing. | Hanqiu Chen, Shao-Peng Yang, Mohammadreza Soltaniyeh, Shuyi Pei, Andrew Chang, Bryan S. Kim, Cong Hao |
| 2025 | ASPDAC | Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEs. | Cong Hao |
| 2025 | FCCM | RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs. | Jiho Kim, Cong Hao |
| 2025 | FCCM | TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs. | Shuyang Li, Hanqing Zhang, Ruiqi Chen, Bruno da Silva, Giorgian Borca-Tasciuc, Dantong Yu, Cong Hao |
| 2025 | ICCAD | LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration. | Ismael Youssef, Hang Yang, Cong Hao |
| 2025 | MICRO | OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs. | Rishov Sarkar, Cong Hao |
| 2024 | DAC | ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model. | Hanqiu Chen, Yitu Wang, Luis Vitorio Cargnini, Mohammadreza Soltaniyeh, Dongyang Li, Gongjin Sun, Pradeep Subedi, Andrew Chang, Yiran Chen, Cong Hao |
| 2024 | FCCM | Ph.D. Project: Modernizing High-Level Hardware Design Workflows. | Rishov Sarkar, Cong Hao |
| 2024 | FCCM | LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization. | Rishov Sarkar, Rachel Paul, Cong Hao |
| 2024 | ICCAD | Residual-INR: Communication Efficient On-Device Learning Using Implicit Neural Representation. | Hanqiu Chen, Xuebin Yao, Pradeep Subedi, Cong Hao |
| 2023 | ASPDAC | Data-Model-Circuit Tri-Design for Ultra-Light Video Intelligence on Edge Devices. | Yimeng Zhang, Akshay Karkal Kamath, Qiucheng Wu, Zhiwen Fan, Wuyang Chen, Zhangyang Wang, Shiyu Chang, Sijia Liu, Cong Hao |
| 2023 | DAC | Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. | Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie |
| 2023 | DATE | M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search. | Akshay Karkal Kamath, Stefan Abi-Karam, Ashwin Bhat, Cong Hao |
| 2023 | FCCM | DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference. | Hanqiu Chen, Cong Hao |
| 2023 | FCCM | Hardware/Software Co-design for Machine Learning Accelerators. | Hanqiu Chen, Cong Hao |
| 2023 | FCCM | LightningSim: Fast and Accurate Trace-Based Simulation for High-Level Synthesis. | Rishov Sarkar, Cong Hao |
| 2023 | FCCM | From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level Synthesis. | Rishov Sarkar, Cong Hao |
| 2023 | FPL | GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization. | Stefan Abi-Karam, Cong Hao |
| 2023 | HPCA | FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference. | Rishov Sarkar, Stefan Abi-Karam, Yuqi He, Lakshmi Sathidevi, Cong Hao |
| 2023 | ICCAD | INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing. | Stefan Abi-Karam, Rishov Sarkar, Dejia Xu, Zhiwen Fan, Zhangyang Wang, Cong Hao |
| 2023 | ICCAD | Rapid-INR: Storage Efficient CPU-Free DNN Training Using Implicit Neural Representation. | Hanqiu Chen, Hang Yang, Stephen B. R. Fitzmeyer, Cong Hao |
| 2023 | ICCAD | Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-Level Sparsity via Mixture-of-Experts. | Rishov Sarkar, Hanxue Liang, Zhiwen Fan, Zhangyang Wang, Cong Hao |
| 2023 | ICCV | Extensible and Efficient Proxy for Neural Architecture Search. | Yuhong Li, Jiajie Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen |
| 2022 | DAC | High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. | Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao |
| 2022 | DAC | H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness. | Xinyi Zhang, Cong Hao, Peipei Zhou, Alex K. Jones, Jingtong Hu |
| 2022 | HPCA | ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. | Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen |
| 2022 | ICCD | AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects. | Nan Wu, Yuan Xie, Cong Hao |
| 2022 | MICCAI | RT-DNAS: Real-Time Constrained Differentiable Neural Architecture Search for 3D Cardiac Cine MRI Segmentation. | Qing Lu, Xiaowei Xu, Shunjie Dong, Cong Hao, Lei Yang, Cheng Zhuo, Yiyu Shi |
| 2021 | DAC | MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. | Lixiang Li, Yao Chen, Zacharie Zirnheld, Pan Li, Cong Hao |
| 2021 | DATE | Workload-Aware Approximate Computing Configuration. | Dongning Ma, Rahul Thapa, Xingjian Wang, Xun Jiao, Cong Hao |
| 2021 | ICLR | HW-NAS-Bench: Hardware-Aware Neural Architecture Search Benchmark. | Chaojian Li, Zhongzhi Yu, Yonggan Fu, Yongan Zhang, Yang Zhao, Haoran You, Qixuan Yu, Yue Wang, Cong Hao, Yingyan Lin |
| 2020 | DAC | EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. | Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen |
| 2020 | FPGA | AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. | Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin |
| 2019 | DAC | FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. | Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen |
| 2019 | FPGA | Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs. | Yao Chen, Jiong He, Xiaofan Zhang, Cong Hao, Deming Chen |
| 2019 | ICCAD | NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. | Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-Mei Hwu, Junli Gu, Deming Chen |
| 2019 | IJCNN | L2Q: An Ultra-Low Loss Quantization Method for DNN Compression. | Cheng Gong, Tao Li, Ye Lu, Cong Hao, Xiaofan Zhang, Deming Chen, Yao Chen |
| 2018 | ECCV | The Sixth Visual Object Tracking VOT2018 Challenge Results. | Matej Kristan, Ales Leonardis, Jiri Matas, Michael Felsberg, Roman P. Pflugfelder, Luka Cehovin Zajc, Toms Vojr, Goutam Bhat, Alan Lukezic, Abdelrahman Eldesokey, Gustavo Fernndez, lvaro Garca-Martn, lvaro Iglesias-Arias, A. Aydin Alatan, Abel Gonzlez-Garca, Alfredo Petrosino, Alireza Memarmoghadam, Andrea Vedaldi, Andrej Muhic, Anfeng He, Arnold W. M. Smeulders, Asanka G. Perera, Bo Li, Boyu Chen, Changick Kim, Changsheng Xu, Changzhen Xiong, Cheng Tian, Chong Luo, Chong Sun, Cong Hao, Daijin Kim, Deepak Mishra, Deming Chen, Dong Wang, Dongyoon Wee, Efstratios Gavves, Erhan Gundogdu, Erik Velasco-Salido, Fahad Shahbaz Khan, Fan Yang, Fei Zhao, Feng Li, Francesco Battistone, George De Ath, Gorthi R. K. Sai Subrahmanyam, Guilherme Sousa Bastos, Haibin Ling, Hamed Kiani Galoogahi, Hankyeol Lee, Haojie Li, Haojie Zhao, Heng Fan, Honggang Zhang, Horst Possegger, Houqiang Li, Huchuan Lu, Hui Zhi, Huiyun Li, Hyemin Lee, Hyung Jin Chang, Isabela Drummond, Jack Valmadre, Jaime Spencer Martin, Javaan Singh Chahl, Jin Young Choi, Jing Li, Jinqiao Wang, Jinqing Qi, Jinyoung Sung, Joakim Johnander, Joo F. Henriques, Jongwon Choi, Joost van de Weijer, Jorge Rodrguez Herranz, Jos M. Martnez, Josef Kittler, Junfei Zhuang, Junyu Gao, Klemen Grm, Lichao Zhang, Lijun Wang, Lingxiao Yang, Litu Rout, Liu Si, Luca Bertinetto, Lutao Chu, Manqiang Che, Mario Edoardo Maresca, Martin Danelljan, Ming-Hsuan Yang, Mohamed H. Abdelpakey, Mohamed Shehata, Myunggu Kang, Namhoon Lee, Ning Wang, Ondrej Miksik, Payman Moallem, Pablo Vicente-Moivar, Pedro Senna, Peixia Li, Philip H. S. Torr, Priya Mariam Raju, Ruihe Qian, Qiang Wang, Qin Zhou, Qing Guo, Rafael Martin Nieto, Rama Krishna Sai Subrahmanyam Gorthi, Ran Tao, Richard Bowden, Richard M. Everson, Runling Wang, Sangdoo Yun, Seokeon Choi, Sergio Vivas, Shuai Bai, Shuangping Huang, Sihang Wu, Simon Hadfield, Siwen Wang, Stuart Golodetz, Ming Tang, Tianyang Xu, Tianzhu Zhang, Tobias Fischer, Vincenzo Santopietro, Vitomir Struc, Wei Wang, Wangmeng Zuo, Wei Feng, Wei Wu, Wei Zou, Weiming Hu, Wengang Zhou, Wenjun Zeng, Xiaofan Zhang, Xiaohe Wu, Xiao-Jun Wu, Xinmei Tian, Yan Li, Yan Lu, Yee Wei Law, Yi Wu, Yiannis Demiris, Yicai Yang, Yifan Jiao, Yuhong Li, Yunhua Zhang, Yuxuan Sun, Zheng Zhang, Zheng Zhu, Zhenhua Feng, Zhihui Wang, Zhiqun He |
| 2013 | ASPDAC | Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis. | Cong Hao, Song Chen, Takeshi Yoshimura |