D. V. Poornaiah
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
1993–1996
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1996 | VLSID | A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. | D. V. Poornaiah, P. V. Ananda Mohan |
| 1995 | VLSID | Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. | D. V. Poornaiah, P. V. Ananda Mohan |
| 1993 | ICASSP | Design and VLSI implementation of a novel concurrent 16-bit multiplier-accumulator for DSP applications. | D. V. Poornaiah, R. Haribabu, M. Omair Ahmad |