| 2024 | ISCA | Determining the Minimum Number of Virtual Networks for Different Coherence Protocols. | Weihang Li, Andrs Goens, Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin |
| 2023 | MICRO | Rigorous Evaluation of Computer Processors with Statistical Model Checking. | Filip Mazurek, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel J. Sorin |
| 2022 | HPCA | HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols. | Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo Olausson, Reece Carr |
| 2022 | ISPASS | Spatiotemporal Strategies for Long-Term FPGA Resource Management. | Atefeh Mehrabi, Daniel J. Sorin, Benjamin C. Lee |
| 2021 | ISPASS | Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures. | Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, Mike O'Connor |
| 2020 | DATE | Prospector: Synthesizing Efficient Accelerators via Statistical Learning. | Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin |
| 2020 | DSN | Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. | Samantha Archer, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin |
| 2020 | IROS | Roadmap Subsampling for Changing Environments. | Sean Murray, George Dimitri Konidaris, Daniel J. Sorin |
| 2020 | ISCA | HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols. | Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin |
| 2019 | DSN | GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. | Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin |
| 2018 | ISCA | ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications. | Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin |
| 2017 | ICCD | Jenga: Efficient Fault Tolerance for Stacked DRAM. | Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin |
| 2017 | MICRO | Architecting hierarchical coherence protocols for push-button parametric verification. | Opeoluwa Matthews, Daniel J. Sorin |
| 2016 | DSN | Methuselah Flash: Rewriting Codes for Extra Long Storage Lifetime. | Georgios Mappouras, Alireza Vahid, A. Robert Calderbank, Daniel J. Sorin |
| 2016 | FMCAD | Verifiable hierarchical protocols with network invariants on parametric systems. | Opeoluwa Matthews, Jesse D. Bingham, Daniel J. Sorin |
| 2016 | MICRO | The microarchitecture of a real-time robot motion planning accelerator. | Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin |
| 2015 | ISPASS | Multi-program benchmark definition. | Adam N. Jacobvitz, Andrew D. Hilton, Daniel J. Sorin |
| 2014 | DAC | Architecting Dynamic Power Management to be Formally Verifiable. | Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang |
| 2014 | DATE | Nostradamus: Low-cost hardware-only error detection for processor cores. | Ralph Nathan, Daniel J. Sorin |
| 2014 | HPCA | Scalably verifiable dynamic power management. | Opeoluwa Matthews, Meng Zhang, Daniel J. Sorin |
| 2014 | HPCA | PVCoherence: Designing flat coherence protocols for scalable verification. | Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin |
| 2014 | SC | Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. | Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun |
| 2013 | HPCA | Coset coding to extend the lifetime of memory. | Adam N. Jacobvitz, A. Robert Calderbank, Daniel J. Sorin |
| 2013 | ISCA | Exploring memory consistency for massively-threaded throughput-oriented processors. | Blake A. Hechtman, Daniel J. Sorin |
| 2013 | ISPASS | Evaluating cache coherent shared virtual memory for heterogeneous multicore chips. | Blake A. Hechtman, Daniel J. Sorin |
| 2013 | PRDC | Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication. | Kushal Seetharam, Lance Ong-Siong Co Ting Keh, Ralph Nathan, Daniel J. Sorin |
| 2011 | DATE | Architectures for online error detection and recovery in multicore processors. | Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, Arijit Biswas, Xavier Vera |
| 2011 | SIGMETRICS | An FPGA-based experimental evaluation of microprocessor core error detection with Argus-2. | Patrick J. Eibl, Albert Meixner, Daniel J. Sorin |
| 2010 | ASPLOS | Specifying and dynamically verifying address translation-aware memory consistency. | Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin |
| 2010 | HPCA | UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. | Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy |
| 2010 | MICRO | Fractal Coherence: Scalably Verifiable Cache Coherence. | Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin |
| 2009 | ISLPED | Dynamic power gating with quality guarantees. | Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin |
| 2009 | MEMOCODE | Multicore power management: Ensuring robustness via early-stage formal verification. | Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen |
| 2008 | DSN | Detouring: Translating software to circumvent hard faults in simple cores. | Albert Meixner, Daniel J. Sorin |
| 2007 | HPCA | Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures. | Albert Meixner, Daniel J. Sorin |
| 2007 | ICCD | Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. | Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz |
| 2007 | MICRO | Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. | Albert Meixner, Michael E. Bauer, Daniel J. Sorin |
| 2006 | DSN | Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures. | Albert Meixner, Daniel J. Sorin |
| 2006 | ICCD | Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. | Nathan Sadler, Daniel J. Sorin |
| 2006 | ITC | Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. | Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin |
| 2006 | SIGMETRICS | Applying architectural vulnerability Analysis to hard faults in the microprocessor. | Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev |
| 2005 | DATE | Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. | Jonathan R. Carter, Sule Ozev, Daniel J. Sorin |
| 2005 | ISCA | Dynamic Verification of Sequential Consistency. | Albert Meixner, Daniel J. Sorin |
| 2005 | MICRO | A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. | Fred A. Bower, Daniel J. Sorin, Sule Ozev |
| 2005 | USENIX | Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution. | Tong Li, Carla Schlatter Ellis, Alvin R. Lebeck, Daniel J. Sorin |
| 2004 | DSN | Tolerating Hard Faults in Microprocessor Array Structures. | Fred A. Bower, Paul G. Shealy, Sule Ozev, Daniel J. Sorin |
| 2004 | ISPASS | Communication breakdown: analyzing CPU usage in commercial Web workloads. | Jaidev P. Patwardhan, Alvin R. Lebeck, Daniel J. Sorin |
| 2003 | DSN | Dynamic Verification of End-to-End Multiprocessor Invariants. | Daniel J. Sorin, Mark D. Hill, David A. Wood |
| 2003 | ISCA | Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. | Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood |
| 2003 | SPAA | Quantifying instruction criticality for shared memory multiprocessors. | Tong Li, Alvin R. Lebeck, Daniel J. Sorin |
| 2002 | HPCA | Bandwidth Adaptive Snooping. | Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, David A. Wood |
| 2002 | ISCA | SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. | Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, David A. Wood |
| 2001 | MICRO | Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. | Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti |
| 2000 | ASPLOS | Timestamp snooping: an approach for extending SMPs. | Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood |
| 2000 | SIGMETRICS | AMVA techniques for high service time variability. | Derek L. Eager, Daniel J. Sorin, Mary K. Vernon |
| 1999 | HPCA | Using Lamport Clocks to Reason about Relaxed Memory Models. | Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin |
| 1999 | ISCA | Multicast Snooping: A New Coherence Method Using a Multicast Address Network. | E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, David A. Wood |
| 1999 | SPAA | A System-Level Specification Framework for I/O Architectures. | Mark D. Hill, Anne Condon, Manoj Plakal, Daniel J. Sorin |
| 1998 | ISCA | Analytic Evaluation of Shared-memory Systems with ILP Processors. | Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood |
| 1998 | SPAA | Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. | Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D. Hill |