Daniel Mueller-Gritschneder
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
44
Venues
17
Active years
2010–2025
Best venue rank
A*
Where they publish
Papers
44 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | CVPR | Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation. | Moritz Thoma, Tobias Preintner, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2025 | CVPR | FLAR-SVD: Fast and Latency-Aware Singular Value Decomposition for Model Compression. | Moritz Thoma, Jorge Villasante, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Mor, Maximilian Groetzinger, Daniil Dylkin, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2025 | DAC | SuperFast: Fast Supernet Training Using Initial Knowledge. | Moritz Thoma, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Mor, Nael Fasfous, Alexander Frickenstein, Manoj Rohit Vemparala, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2025 | DATE | Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. | Johannes Geier, Leonidas Kontopoulos, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2025 | DATE | HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization. | Shambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Mor, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2025 | IJCNN | Automated Graph-level Passes for TinyML Fault Tolerance. | Johannes Kappes, Johannes Geier, Phillipp van Kempen, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2025 | IJCNN | DRIP: DRop unImportant data Points - Enhancing Machine Learning Efficiency with Grad-CAM-Based Streaming Data Prioritization for On-Device Training. | Marcus Rb, Daniel Konegen, Axel Sikora, Daniel Mueller-Gritschneder |
| 2024 | DATE | MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. | Pierpaolo Mor, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2024 | DSD | Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. | Philipp van Kempen, Mathis Salmen, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2024 | ECCV | EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation. | Nikolai Krber, Eduard Kromer, Andreas Siebert, Sascha Hauke, Daniel Mueller-Gritschneder, Bjrn W. Schuller |
| 2024 | IJCNN | Advancing On-Device Neural Network Training with TinyPropv2: Dynamic, Sparse, and Efficient Backpropagation. | Marcus Rb, Axel Sikora, Daniel Mueller-Gritschneder |
| 2024 | WACV | Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge. | Pierpaolo Mor, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone |
| 2023 | ASPDAC | CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V. | Johannes Geier, Lukas Auer, Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann |
| 2023 | DATE | Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems. | Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jrg Henkel, Ulf Schlichtmann |
| 2023 | DATE | Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications. | Uzair Sharif, Daniel Mueller-Gritschneder, Rafael Stahl, Ulf Schlichtmann |
| 2023 | ECRTS | Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs. | Ahsan Saeed, Denis Hoornaert, Dakshina Dasari, Dirk Ziegenbein, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Andreas Gerstlauer, Renato Mancuso |
| 2022 | DATE | The Scale4Edge RISC-V Ecosystem. | Wolfgang Ecker, Peer Adelt, Wolfgang Mller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jrg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz |
| 2022 | FDL | CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation. | Conrad Foik, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2022 | MODELSWARD | Universal Safety Format: Automated Safety Software Generation. | Frederik Haxel, Alexander Viehl, Michael Benkel, Bjoern Beyreuther, Klaus Birken, Rolf Schmedes, Kim Grttner, Daniel Mueller-Gritschneder |
| 2022 | RTAS | Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores. | Ahsan Saeed, Dakshina Dasari, Dirk Ziegenbein, Varun Rajasekaran, Falk Rehm, Michael Pressler, Arne Hamann, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann |
| 2021 | ICMLA | Tiny Generative Image Compression for Bandwidth-Constrained Sensor Applications. | Nikolai Krber, Andreas Siebert, Sascha Hauke, Daniel Mueller-Gritschneder |
| 2020 | ASPDAC | Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation. | Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2020 | VLSID | Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. | Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2019 | ASPDAC | SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. | Petra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2019 | DAC | Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. | Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, Subhasish Mitra |
| 2019 | DATE | SRAM Design Exploration with Integrated Application-Aware Aging Analysis. | Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Sani R. Nassif |
| 2018 | DATE | Design and validation of fault-tolerant embedded controllers. | Saurav Kumar Ghosh, Soumyajit Dey, Dip Goswami, Daniel Mueller-Gritschneder, Samarjit Chakraborty |
| 2018 | DATE | ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. | Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann |
| 2018 | FDL | Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation. | Rafael Stahl, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2018 | ICCAD | Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search. | Yong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2018 | ICCAD | Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML. | Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann |
| 2018 | IOLTS | Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping. | Alexandra Listl, Daniel Mueller-Gritschneder, Fabian Kluge, Ulf Schlichtmann |
| 2018 | IOLTS | Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary. | Petra R. Maier, Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2017 | RSP | The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. | Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann |
| 2015 | DATE | The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. | Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh |
| 2013 | ASPDAC | Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software. | Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2013 | DATE | Fast cache simulation for host-compiled simulation of embedded software. | Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2013 | DATE | Analytical timing estimation for temporally decoupled TLMs considering resource conflicts. | Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2013 | DATE | A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot. | Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann |
| 2013 | DATE | A spectral clustering approach to application-specific network-on-chip synthesis. | Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann |
| 2012 | DATE | Accurately timed transaction level models for virtual prototyping at high abstraction level. | Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
| 2012 | DATE | Automated construction of a cycle-approximate transaction level model of a memory controller. | Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann |
| 2011 | DSD | Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level. | Daniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann |
| 2010 | DATE | Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. | Daniel Mueller-Gritschneder, Helmut Graeb |