David Trilla
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
7
Active years
2016–2024
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | HPCA | Enterprise-Class Cache Compression Design. | Alper Buyuktosunoglu, David Trilla, Blent Abali, Deanna Postles Dunn Berger, Craig R. Walters, Jang-Soo Lee |
| 2021 | ETS | SafeSU: an Extended Statistics Unit for Multicore Timing Interference. | Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide, Miquel Moret, Carles Hernndez, Jaume Abella |
| 2021 | IOLTS | SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping. | Francisco Bas, Sergi Alcaide, Ruben Lorenzo, Guillem Cabo, Guillermo Gil, Oriol Sala, Fabio Mazzocchetti, David Trilla, Jaume Abella |
| 2021 | IOLTS | SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation. | Oriol Sala, Sergi Alcaide, Guillem Cabo, Francisco Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Guillermo Gil, Fabio Mazzocchetti, Jaume Abella |
| 2021 | MICRO | NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators. | David Trilla, John-David Wellman, Alper Buyuktosunoglu, Pradip Bose |
| 2019 | DSD | An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2019 | DSD | Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2018 | DAC | Cache side-channel attacks and time-predictability in high-performance critical real-time systems. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2016 | IOLTS | Resilient random modulo cache memories for probabilistically-analyzable real-time systems. | David Trilla, Carles Hernndez, Jaume Abella, Francisco J. Cazorla |
| 2016 | RTAS | Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems. | David Trilla, Javier Jalle, Mikel Fernndez, Jaume Abella, Francisco J. Cazorla |