| 1999 | ALENEX | Heuristics and Experimental Design for Bigraph Crossing Number Minimization. | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh |
| 1999 | ISCAS | Equivalence classes of circuit mutants for experimental design. | Debabrata Ghosh, Franc Brglez |
| 1999 | ISCAS | Evaluating iterative improvement heuristics for bigraph crossing minimization. | Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh |
| 1998 | DATE | Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. | Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III |
| 1995 | VLSID | Wave pipelined architecture folding: a method to achieve low power and low area. | Debabrata Ghosh, Soumitra Kumar Nandy |
| 1994 | VLSID | TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy |
| 1994 | VLSID | A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. | Debabrata Ghosh, Shamik Sural, S. K. Nandy |
| 1993 | DAC | Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. | Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy |
| 1993 | ICCD | A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. | Debabrata Ghosh, S. K. Nandy |
| 1993 | VLSID | NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan |