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Paper
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell.
Debabrata Ghosh
,
Shamik Sural
,
S. K. Nandy
Venue
National
VLSID
Year
1994
Proceedings
VLSI Design
DBLP record
conf/vlsid/GhoshSN94 ↗
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