| 2019 | VLSID | A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers |
| 2019 | VLSID | Applying Modified Householder Transform to Kalman Filter. | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers |
| 2018 | VLSID | Design Space Exploration of an Execution-Driven Functional Simulation Methodology. | Ipsita Biswas Mahapatra, Utkarsh Agarwal, Chandrashekhar Azad, S. K. Nandy |
| 2017 | CASES | REDEFINE | Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, Franois Neumann, Philippe Baufreton |
| 2016 | VLSID | VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. | Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan |
| 2016 | VLSID | Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. | Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan |
| 2016 | VLSID | Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan |
| 2015 | HPCC | Compiling HPC Kernels for the REDEFINE CGRA. | Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan |
| 2015 | VLSID | Hardware Solution for Real-Time Face Recognition. | Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan |
| 2015 | VLSID | Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. | Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan |
| 2015 | VLSID | A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. | Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya |
| 2015 | SERVICES | Location Obfuscation for Location Data Privacy. | Vaibhav Ankush Kachore, J. Lakshmi, S. K. Nandy |
| 2014 | VLSID | Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). | Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan |
| 2013 | CloudCom | Virtual Machine Placement Optimization Supporting Performance SLAs. | Ankit Anand, J. Lakshmi, S. K. Nandy |
| 2013 | ISCAS | High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. | S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan |
| 2013 | VLSID | Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors. | Abhijit Giri, S. K. Nandy |
| 2011 | SECRYPT | A Method for Flexible Reduction over Binary Fields using a Field Multiplier. | Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy |
| 2010 | CASES | Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. | Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita |
| 2009 | CASES | Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. | Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan |
| 2009 | GPC | I/O Device Virtualization in the Multi-core era, a QoS Perspective. | J. Lakshmi, S. K. Nandy |
| 2007 | ASPDAC | Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. | Subhasis Banerjee, G. Surendra, S. K. Nandy |
| 2007 | FPL | REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. | A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan |
| 2006 | AINA | A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. | K. Kalapriya, S. K. Nandy, Nanjangud C. Narendra |
| 2006 | ISPA | Framework for Enabling Highly Available Distributed Applications for Utility Computing. | J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan |
| 2006 | MICRO | Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. | Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell |
| 2005 | AINA | Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. | K. Kalapriya, S. K. Nandy |
| 2005 | Middleware | Functional and architectural adaptation in pervasive computing environments. | Nanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya |
| 2004 | AINA | Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? | K. Kalapriya, S. K. Nandy, K. Venkatesh Babu |
| 2004 | ASPDAC | Exploiting program execution phases to trade power and performance for media workload. | Subhasis Banerjee, G. Surendra, S. K. Nandy |
| 2004 | ASPDAC | Power-performance trade-off using pipeline delays. | G. Surendra, Subhasis Banerjee, S. K. Nandy |
| 2003 | DAC | A complexity effective communication model for behavioral modeling of signal processing applications. | M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy |
| 2003 | DATE | Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. | G. Surendra, Subhasis Banerjee, S. K. Nandy |
| 2003 | ISLPED | Multivoltage scheduling with voltage-partitioned variable storage. | Amitabh Menon, S. K. Nandy, Mahesh Mehendale |
| 2002 | EuroPar | Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). | H. Sarojadevi, S. K. Nandy, Srinivasan Balakrishnan |
| 2002 | ICCD | Speculative Trace Scheduling in VLIW Processors. | Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan |
| 2002 | PDPTA | On the Benefits of Speculative Trace Scheduling in VLIW Processors. | Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan |
| 2001 | ISCAS | Content adaptive motion estimation for mobile video encoders. | Arshad Ahmed, S. K. Nandy, Paul Sathya |
| 2001 | VLSID | Architecture of Reconfigurable a Low Power Gigabit AT Switch. | Abhijit M. Lele, S. K. Nandy |
| 2001 | VLSID | ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. | G. Surendra, S. K. Nandy, Paul Sathya |
| 2000 | DAC | Power minimization using control generated clocks. | M. Srikanth Rao, S. K. Nandy |
| 1999 | HiPC | Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. | Abhijit M. Lele, S. K. Nandy |
| 1999 | ICCD | Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. | Avinash K. Gautam, V. Visvanathan, S. K. Nandy |
| 1999 | VLSID | Synthesis of Configurable Architectures for DSP Algorithms. | S. Ramanathan, V. Visvanathan, S. K. Nandy |
| 1997 | HiPC | Modeling multi-threaded architectures in PAMELA for real-time high performance applications. | Srinivasan Balakrishnan, S. K. Nandy, Arjan J. C. van Gemund |
| 1994 | VLSID | TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy |
| 1994 | VLSID | A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. | Debabrata Ghosh, Shamik Sural, S. K. Nandy |
| 1994 | VLSID | High Speed Digital Filtering on SRAM-Based FPGAs. | Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal |
| 1994 | VLSID | A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. | G. N. Rathna, S. K. Nandy, K. Parthasarathy |
| 1993 | DAC | Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. | Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy |
| 1993 | ICCD | A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. | Debabrata Ghosh, S. K. Nandy |
| 1993 | ICPP | A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. | S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan |
| 1993 | VLSID | NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan |
| 1989 | DAC | Special Purpose Architecture for Accelerating Bitmap DRC. | Narasimha B. Bhat, S. K. Nandy |
| 1986 | DAC | Dual quadtree representation for VLSI designs. | S. K. Nandy, L. V. Ramakrishnan |