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Paper
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs.
G. N. Rathna
,
S. K. Nandy
,
K. Parthasarathy
Venue
National
VLSID
Year
1994
Proceedings
VLSI Design
DBLP record
conf/vlsid/RathnaNP94 ↗
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