K. Parthasarathy
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
1993–1994
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1994 | VLSID | TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy |
| 1994 | VLSID | A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. | G. N. Rathna, S. K. Nandy, K. Parthasarathy |
| 1993 | DAC | Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. | Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy |
| 1993 | VLSID | NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan |