| 2022 | VLSID | Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. | Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh K. Das, Bhargab B. Bhattacharya |
| 2015 | DDECS | Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. | Joyati Mondal, Bappaditya Mondal, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das |
| 2013 | RC | Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. | Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler |
| 2005 | ASPDAC | Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. | Hafizur Rahaman, Debesh K. Das |
| 2005 | VLSID | Cellular Automata Based Test Structures with Logic Folding. | Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das |
| 2004 | ASPDAC | Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. | Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya |
| 2004 | VLSID | Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. | Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya |
| 2002 | VLSID | A New Synthesis of Symmetric Functions. | Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya |
| 2002 | VLSID | Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. | Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das |
| 2001 | ASPDAC | Cellular automata as a built in self test structure. | Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri |
| 2001 | VLSID | Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. | Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly |
| 1999 | ASPDAC | An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. | Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya |
| 1999 | VLSID | Synthesis of Symmetric Functions for Path-Delay Fault Testability. | Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya |
| 1998 | ASPDAC | Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. | Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya |
| 1998 | VLSID | Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
| 1996 | VTS | Isomorph-redundancy in sequential circuits. | Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya |